PIC24HJ64 Datasheet

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PIC24HJ32GP302/304, <strong>PIC24HJ64</strong>GPX02/X04, AND PIC24HJ128GPX02/X04 FIGURE 19-3: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM AD1CON3 ADC Internal RC Clock (2) AD1CON3 0 1 TAD 6 TOSC (1) X2 TCY ADC Conversion Clock Multiplier 1, 2, 3, 4, 5,..., 64 Note 1: Refer to Figure 8-2 for the derivation of Fosc when the PLL is enabled. If the PLL is not used, Fosc is equal to the clock source frequency. Tosc = 1/Fosc 2: See the ADC electrical characteristics for the exact RC clock value. DS70293B-page 216 Preliminary © 2008 Microchip Technology Inc.
PIC24HJ32GP302/304, <strong>PIC24HJ64</strong>GPX02/X04, AND PIC24HJ128GPX02/X04 REGISTER 19-1: AD1CON1: ADC1 CONTROL REGISTER 1 R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 ADON — ADSIDL ADDMABM — AD12B FORM bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 HC,HS R/C-0 HC, HS SSRC — SIMSAM ASAM SAMP DONE bit 7 bit 0 Legend: HC = Cleared by hardware HS = Set by hardware R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 ADON: ADC Operating Mode bit 1 = ADC module is operating 0 = ADC is off bit 14 Unimplemented: Read as ‘0’ bit 13 ADSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12 ADDMABM: DMA Buffer Build Mode bit 1 = DMA buffers are written in the order of conversion. The module provides an address to the DMA channel that is the same as the address used for the non-DMA stand-alone buffer. 0 = DMA buffers are written in Scatter/Gather mode. The module provides a scatter/gather address to the DMA channel, based on the index of the analog input and the size of the DMA buffer. bit 11 Unimplemented: Read as ‘0’ bit 10 bit 9-8 AD12B: 10-bit or 12-bit Operation Mode bit 1 = 12-bit, 1-channel ADC operation 0 = 10-bit, 4-channel ADC operation FORM: Data Output Format bits For 10-bit operation: 11 = Reserved 10 = Reserved 01 = Signed integer (DOUT = ssss sssd dddd dddd, where s = .NOT.d) 00 = Integer (DOUT = 0000 00dd dddd dddd) For 12-bit operation: 11 = Reserved 10 = Reserved 01 = Signed Integer (DOUT = ssss sddd dddd dddd, where s = .NOT.d) 00 = Integer (DOUT = 0000 dddd dddd dddd) bit 7-5 SSRC: Sample Clock Source Select bits 111 = Internal counter ends sampling and starts conversion (auto-convert) 110 = Reserved 101 = Reserved 100 = GP timer (Timer5 for ADC1) compare ends sampling and starts conversion 011 = Reserved 010 = GP timer (Timer3 for ADC1) compare ends sampling and starts conversion 001 = Active transition on INT pin ends sampling and starts conversion 000 = Clearing sample bit ends sampling and starts conversion bit 4 Unimplemented: Read as ‘0’ © 2008 Microchip Technology Inc. Preliminary DS70293B-page 217
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