PIC24HJ64 Datasheet

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PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, AND PIC24HJ128GPX02/X04 2.5 Arithmetic Logic Unit (ALU) The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, and PIC24HJ128GPX02/X04 ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are two’s complement in nature. Depending on the operation, the ALU can affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC Status bits operate as Borrow and Digit Borrow bits, respectively, for subtraction operations. The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. Refer to the “dsPIC30F/33F Programmer’s Reference Manual” (DS70157) for information on the SR bits affected by each instruction. The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, and PIC24HJ128GPX02/X04 CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and support hardware for 16-bit-divisor division. 2.5.1 MULTIPLIER Using the high-speed 17-bit x 17-bit multiplier, the ALU supports unsigned, signed or mixed-sign operation in several MCU multiplication modes: • 16-bit x 16-bit signed • 16-bit x 16-bit unsigned • 16-bit signed x 5-bit (literal) unsigned • 16-bit unsigned x 16-bit unsigned • 16-bit unsigned x 5-bit (literal) unsigned • 16-bit unsigned x 16-bit signed • 8-bit unsigned x 8-bit unsigned 2.5.2 DIVIDER The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: 1. 32-bit signed/16-bit signed divide 2. 32-bit unsigned/16-bit unsigned divide 3. 16-bit signed/16-bit signed divide 4. 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends up in W0 and the remainder in W1. 16-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. 2.5.3 MULTI-BIT DATA SHIFTER The multi-bit data shifter is capable of performing up to 16-bit arithmetic or logic right shifts, or up to 16-bit left shifts in a single cycle. The source can be either a working register or a memory location. The shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. A positive value shifts the operand right. A negative value shifts the operand left. A value of ‘0’ does not modify the operand. DS70293B-page 18 Preliminary © 2008 Microchip Technology Inc.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, AND PIC24HJ128GPX02/X04 3.0 MEMORY ORGANIZATION Note: This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, and PIC24HJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the PIC24H Family Reference Manual, “Section 4. Program Memory” (DS70238), which is available from the Microchip website (www.microchip.com). The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, and PIC24HJ128GPX02/X04 architecture features separate program and data memory spaces and buses. This architecture also allows the direct access of program memory from the data space during code execution. 3.1 Program Address Space The program address memory space of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, and PIC24HJ128GPX02/X04 devices is 4M instructions. The space is addressable by a 24-bit value derived either from the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping as described in Section 3.4 “Interfacing Program and Data Memory Spaces”. User application access to the program memory space is restricted to the lower half of the address range (0x000000 to 0x7FFFFF). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG to permit access to the Configuration bits and Device ID sections of the configuration memory space. The memory map for the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, and PIC24HJ128GPX02/X04 devices is shown in Figure 3-1. FIGURE 3-1: PROGRAM MEMORY MAP FOR PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, AND PIC24HJ128GPX02/X04 DEVICES Configuration Memory Space User Memory Space Note: PIC24HJ32GP302/304 GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table User Program Flash Memory (11264 instructions) Unimplemented (Read ‘0’s) Reserved Device Configuration Registers Reserved DEVID (2) Memory areas are not shown to scale. PIC24HJ64GPX02/X04 GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table User Program Flash Memory (22016 instructions) Unimplemented (Read ‘0’s) Reserved Device Configuration Registers Reserved DEVID (2) PIC24HJ128GPX02/X04 GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table User Program Flash Memory (44032 instructions) Unimplemented (Read ‘0’s) Reserved Device Configuration Registers Reserved DEVID (2) Reserved Reserved Reserved 0x000000 0x000002 0x000004 0x0000FE 0x000100 0x000104 0x0001FE 0x000200 0x0057FE 0x005800 0x00ABFE 0x00AC00 0x0157FE 0x015800 0x7FFFFE 0x800000 0xF7FFFE 0xF80000 0xF80017 0xF80018 0xFEFFFE 0xFF0000 0xFF0002 0xFFFFFE © 2008 Microchip Technology Inc. Preliminary DS70293B-page 19
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