PIC24HJ64 Datasheet

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PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, AND PIC24HJ128GPX02/X04 FIGURE 19-1: ADC MODULE BLOCK DIAGRAM VREF+ (1) VREF- (1) AVDD AVSS AN0 AN0 AN3 AN6 AN9 VREF- + S/H - CH1 (2) ADC1 AN1 AN2 AN1 AN4 AN7 AN10 VREF- AN2 AN5 AN8 AN11 VREF- + CH2 (2) S/H - + CH3 (2) S/H - Sample CH1,CH2, CH3,CH0 Conversion Result Conversion Logic 16-bit ADC Output Buffer Sample/Sequence Control Data Format Bus Interface AN3 00000 00001 00010 00011 Input Switches Input MUX Control AN4 00100 AN5 00101 AN6 00110 AN7 00111 AN8 01000 AN9 01001 AN10 01010 AN11 01011 AN12 01100 VREF- AN1 + S/H - CH0 Note 1: VREF+, VREF- inputs can be multiplexed with other analog inputs. 2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation. DS70293B-page 214 Preliminary © 2008 Microchip Technology Inc.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, AND PIC24HJ128GPX02/X04 FIGURE 19-2: ADC1 MODULE BLOCK DIAGRAM FOR PIC24HJ32GP302, PIC24HJ64GP202/ 502, AND PIC24HJ128GP202/502 DEVICES VREF+ (1) VREF- (1) AVDD AVSS AN0 AN0 AN3 AN9 VREF- + S/H - CH1 (2) ADC1 AN1 AN2 AN1 AN4 AN10 VREF- AN2 AN5 AN11 VREF- + CH2 (2) S/H - + CH3 (2) S/H - Sample CH1,CH2, CH3,CH0 Conversion Result Conversion Logic 16-bit ADC Output Buffer Sample/Sequence Control Data Format Bus Interface AN3 00000 00001 00010 00011 Input Switches Input MUX Control AN4 00100 AN5 00101 AN9 01001 AN10 01010 AN11 01011 AN12 01100 VREF- AN1 + S/H - CH0 Note 1: VREF+, VREF- inputs may be multiplexed with other analog inputs. 2: Channels 1, 2 and 3 are not applicable for the 12-bit mode of operation. © 2008 Microchip Technology Inc. Preliminary DS70293B-page 215
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