PIC24HJ64 Datasheet

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PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, AND PIC24HJ128GPX02/X04 5.7 Configuration Mismatch Reset To maintain the integrity of the peripheral pin select control registers, they are constantly monitored with shadow registers in hardware. If an unexpected change in any of the registers occur (such as cell disturbances caused by ESD or other external events), a configuration mismatch Reset occurs. The Configuration Mismatch Flag (CM) bit in the Reset Control (RCON) register is set to indicate the configuration mismatch Reset. Refer to Section 10.0 “I/O Ports” for more information on the configuration mismatch Reset. Note: The configuration mismatch feature and associated reset flag is not available on all devices. 5.8 Illegal Condition Device Reset An illegal condition device Reset occurs due to the following sources: • Illegal Opcode Reset • Uninitialized W Register Reset • Security Reset The Illegal Opcode or Uninitialized W Access Reset Flag (IOPUWR) bit in the Reset Control (RCON) register is set to indicate the illegal condition device Reset. 5.8.0.1 ILLEGAL OPCODE RESET A device Reset is generated if the device attempts to execute an illegal opcode value that is fetched from program memory. The illegal opcode Reset function can prevent the device from executing program memory sections that are used to store constant data. To take advantage of the illegal opcode Reset, use only the lower 16 bits of each program memory section to store the data values. The upper 8 bits should be programmed with 3Fh, which is an illegal opcode value. 5.8.0.2 UNINITIALIZED W REGISTER RESET Any attempts to use the uninitialized W register as an address pointer will Reset the device. The W register array (with the exception of W15) is cleared during all resets and is considered uninitialized until written to. 5.8.0.3 SECURITY RESET If a Program Flow Change (PFC) or Vector Flow Change (VFC) targets a restricted location in a protected segment (Boot and Secure Segment), that operation will cause a security Reset. The PFC occurs when the Program Counter is reloaded as a result of a Call, Jump, Computed Jump, Return, Return from Subroutine, or other form of branch instruction. The VFC occurs when the Program Counter is reloaded with an Interrupt or Trap vector. Refer to Section 24.8 “Code Protection and CodeGuard Security” for more information on Security Reset. 5.9 Using the RCON Status Bits The user application can read the Reset Control (RCON) register after any device Reset to determine the cause of the reset. Note: The status bits in the RCON register should be cleared after they are read so that the next RCON register value after a device Reset will be meaningful. Table 5-3 provides a summary of the reset flag bit operation. TABLE 5-3: RESET FLAG BIT OPERATION Flag Bit Set by: Cleared by: TRAPR (RCON) Trap conflict event POR,BOR IOPWR (RCON) Illegal opcode or uninitialized POR,BOR W register access or Security Reset CM (RCON) Configuration Mismatch POR,BOR EXTR (RCON) MCLR Reset POR SWR (RCON) RESET instruction POR,BOR WDTO (RCON) WDT time-out PWRSAV instruction, CLRWDT instruction, POR,BOR SLEEP (RCON) PWRSAV #SLEEP instruction POR,BOR IDLE (RCON) PWRSAV #IDLE instruction POR,BOR BOR (RCON) POR, BOR POR (RCON) POR Note: All Reset flag bits can be set or cleared by user software. DS70293B-page 60 Preliminary © 2008 Microchip Technology Inc.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, AND PIC24HJ128GPX02/X04 6.0 INTERRUPT CONTROLLER Note: This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, and PIC24HJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the PIC24H Family Reference Manual, “Section 6. Interrupts” (DS70224), which is available from the Microchip website (www.microchip.com). The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, and PIC24HJ128GPX02/X04 interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, and PIC24HJ128GPX02/X04 CPU. The interrupt controller has the following features: • Up to eight processor exceptions and software traps • Eight user-selectable priority levels • Interrupt Vector Table (IVT) with up to 118 vectors • A unique vector for each interrupt or exception source • Fixed priority within a specified user priority level • Alternate Interrupt Vector Table (AIVT) for debug support • Fixed interrupt entry and return latencies 6.1 Interrupt Vector Table The Interrupt Vector Table (IVT), shown in Figure 6-1, resides in program memory, starting at location 000004h. The IVT contains 126 vectors consisting of eight nonmaskable trap vectors plus up to 118 sources of interrupt. In general, each interrupt source has its own vector. Each interrupt vector contains a 24-bitwide address. The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR). Interrupt vectors are prioritized in terms of their natural priority. This priority is linked to their position in the vector table. Lower addresses generally have a higher natural priority. For example, the interrupt associated with vector 0 takes priority over interrupts at any other vector address. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, and PIC24HJ128GPX02/X04 devices implement up to 45 unique interrupts and five nonmaskable traps. These are summarized in Table 6-1. 6.1.1 ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 6-1. Access to the AIVT is provided by the ALTIVT control bit (INTCON2). If the ALTIVT bit is set, all interrupt and exception processes use the alternate vectors instead of the default vectors. The alternate vectors are organized in the same manner as the default vectors. The AIVT supports debugging by providing a means to switch between an application and a support environment without requiring the interrupt vectors to be reprogrammed. This feature also enables switching between applications for evaluation of different software algorithms at run time. If the AIVT is not needed, the AIVT should be programmed with the same addresses used in the IVT. 6.2 Reset Sequence A device Reset is not a true exception because the interrupt controller is not involved in the Reset process. The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, and PIC24HJ128GPX02/X04 device clears its registers in response to a Reset, which forces the PC to zero. The microcontroller then begins program execution at location 0x000000. A GOTO instruction at the Reset address can redirect program execution to the appropriate start-up routine. Note: Any unimplemented or unused vector locations in the IVT and AIVT should be programmed with the address of a default interrupt handler routine that contains a RESET instruction. © 2008 Microchip Technology Inc. Preliminary DS70293B-page 61
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PIC24HJ64 Datasheet

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