PIC24HJ64 Datasheet

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PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, AND PIC24HJ128GPX02/X04 TABLE 3-32: SECURITY REGISTER MAP (1) File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets BSRAM 0750 — — — — — — — — — — — — — IW_BSR IR_BSR RL_BSR 0000 SSRAM 0752 — — — — — — — — — — — — — IW_ SSR IR_SSR RL_SSR 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: This register is not present in devices with 32K Flash (PIC24HJ32GP302/304). TABLE 3-33: NVM REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets NVMCON 0760 WR WREN WRERR — — — — — — ERASE — — NVMOP 0000 NVMKEY 0766 — — — — — — — — NVMKEY 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-34: PMD REGISTER MAP File Name Addr Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets PMD1 0770 T5MD T4MD T3MD T2MD T1MD — — — I2C1MD U2MD U1MD SPI2MD SPI1MD — C1MD AD1MD 0000 PMD2 0772 IC8MD IC7MD — — — — IC2MD IC1MD — — — — OC4MD OC3MD OC2MD OC1MD 0000 PMD3 0774 — — — — — CMPMD RTCCMD PMPMD CRCMD — — — — — — — 0000 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. DS70293B-page 40 Preliminary © 2008 Microchip Technology Inc.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, AND PIC24HJ128GPX02/X04 3.2.6 SOFTWARE STACK In addition to its use as a working register, the W15 register in the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, and PIC24HJ128GPX02/X04 devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It predecrements for stack pops and post-increments for stack pushes, as shown in Figure 3-5. For a PC push during any CALL instruction, the MSb of the PC is zeroextended before the push, ensuring that the MSb is always clear. Note: The Stack Pointer Limit register (SPLIM) associated with the Stack Pointer sets an upper address boundary for the stack. SPLIM is uninitialized at Reset. As is the case for the Stack Pointer, SPLIM is forced to ‘0’ because all stack operations must be word aligned. Whenever an EA is generated using W15 as a source or destination pointer, the resulting address is compared with the value in SPLIM. If the contents of the Stack Pointer (W15) and the SPLIM register are equal and a push operation is performed, a stack error trap does not occur. The stack error trap occurs on a subsequent push operation. For example, to cause a stack error trap when the stack grows beyond address 0x2000 in RAM, initialize the SPLIM with the value 0x1FFE. Similarly, a Stack Pointer underflow (stack error) trap is generated when the Stack Pointer address is found to be less than 0x0800. This prevents the stack from interfering with the Special Function Register (SFR) space. A write to the SPLIM register should not be immediately followed by an indirect read operation using W15. FIGURE 3-5: 0x0000 Stack Grows Toward Higher Address A PC push during exception processing concatenates the SRL register to the MSb of the PC prior to the push. 15 PC 000000000 PC CALL STACK FRAME 0 W15 (before CALL) W15 (after CALL) POP : [--W15] PUSH : [W15++] 3.2.7 DATA RAM PROTECTION FEATURE The PIC24H product family supports Data RAM protection features that enable segments of RAM to be protected when used in conjunction with Boot and Secure Code Segment Security. BSRAM (Secure RAM segment for BS) is accessible only from the Boot Segment Flash code when enabled. SSRAM (Secure RAM segment for RAM) is accessible only from the Secure Segment Flash code when enabled. See Table 3-1 for an overview of the BSRAM and SSRAM SFRs. 3.3 Instruction Addressing Modes The addressing modes shown in Table 3-35 form the basis of the addressing modes optimized to support the specific features of individual instructions. The addressing modes provided in the MAC class of instructions differ from those in the other instruction types. 3.3.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space). Most file register instructions employ a working register, W0, which is denoted as WREG in these instructions. The destination is typically either the same file register or WREG (with the exception of the MUL instruction), which writes the result to a register or register pair. The MOV instruction allows additional flexibility and can access the entire data space. 3.3.2 MCU INSTRUCTIONS The three-operand MCU instructions are of the form: Operand 3 = Operand 1 Operand 2 where Operand 1 is always a working register (that is, the addressing mode can only be register direct), which is referred to as Wb. Operand 2 can be a W register, fetched from data memory, or a 5-bit literal. The result location can be either a W register or a data memory location. The following addressing modes are supported by MCU instructions: • Register Direct • Register Indirect • Register Indirect Post-Modified • Register Indirect Pre-Modified • 5-bit or 10-bit Literal Note: Not all instructions support all the addressing modes given above. Individual instructions can support different subsets of these addressing modes. © 2008 Microchip Technology Inc. Preliminary DS70293B-page 41
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PIC24HJ64 Datasheet

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