PIC24HJ64 Datasheet

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PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, AND PIC24HJ128GPX02/X04 TABLE 24-5: CODE FLASH SECURITY SEGMENT SIZES FOR 128K BYTE DEVICES CONFIG BITS BSS = x11 0K BSS = x10 1K BSS = x01 4K BSS = x00 8K SSS = x11 0K VS = 256 IW GS = 43776 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh VS = 256 IW BS = 768 IW GS = 43008 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh VS = 256 IW BS = 3840 IW GS = 39936 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh VS = 256 IW BS = 7936 IW GS = 35840 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh SSS = x10 4K VS = 256 IW SS = 3840 IW GS = 39936 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh VS = 256 IW BS = 768 IW SS = 3072 IW GS = 39936 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh VS = 256 IW BS = 3840 IW GS = 39936 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh VS = 256 IW BS = 7936 IW GS = 35840 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh SSS = x01 8K VS = 256 IW SS = 7936 IW GS = 35840 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh VS = 256 IW BS = 768 IW SS = 7168 IW GS = 35840 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh VS = 256 IW BS = 3840 IW SS = 4096 IW GS = 35840 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh VS = 256 IW BS = 7936 IW GS = 35840 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh SSS = x00 16K VS = 256 IW SS = 16128 IW GS = 27648 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh VS = 256 IW BS = 768 IW SS = 15360 IW GS = 27648 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh VS = 256 IW BS = 3840 IW SS = 12288 IW GS = 27648 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh VS = 256 IW BS = 7936 IW SS = 8192 IW GS = 27648 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh DS70293B-page 262 Preliminary © 2008 Microchip Technology Inc.
PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, AND PIC24HJ128GPX02/X04 25.0 INSTRUCTION SET SUMMARY Note: This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04, and PIC24HJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section in the PIC24H Family Reference Manual, which is available from the Microchip website (www.microchip.com). The PIC24H instruction set is identical to that of the PIC24F, and is a subset of the dsPIC30F/33F instruction set. Most instructions are a single program memory word (24 bits). Only three instructions require two program memory locations. Each single-word instruction is a 24-bit word, divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into five basic categories: • Word or byte-oriented operations • Bit-oriented operations • Literal operations • Control operations Table 25-1 shows the general symbols used in describing the instructions. The PIC24H instruction set summary in Table 25-2 lists all the instructions, along with the status flags affected by each instruction. Most word or byte-oriented W register instructions (including barrel shift instructions) have three operands: • The first source operand which is typically a register ‘Wb’ without any address modifier • The second source operand which is typically a register ‘Ws’ with or without an address modifier • The destination of the result which is typically a register ‘Wd’ with or without an address modifier However, word or byte-oriented file register instructions have two operands: • The file register specified by the value ‘f’ • The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ Most bit-oriented instructions (including simple rotate/shift instructions) have two operands: • The W register (with or without an address modifier) or file register (specified by the value of ‘Ws’ or ‘f’) • The bit in the W register or file register (specified by a literal value or indirectly by the contents of register ‘Wb’) The literal instructions that involve data movement may use some of the following operands: • A literal value to be loaded into a W register or file register (specified by the value of ‘k’) • The W register or file register where the literal value is to be loaded (specified by ‘Wb’ or ‘f’) However, literal instructions that involve arithmetic or logical operations use some of the following operands: • The first source operand which is a register ‘Wb’ without any address modifier • The second source operand which is a literal value • The destination of the result (only if not the same as the first source operand) which is typically a register ‘Wd’ with or without an address modifier The control instructions may use some of the following operands: • A program memory address • The mode of the table read and table write instructions All instructions are a single word, except for certain double word instructions, which were made double word instructions so that all the required information is available in these 48 bits. In the second word, the 8MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA (unconditional/computed branch), indirect CALL/GOTO, all table reads and writes and RETURN/RETFIE instructions, which are single-word instructions but take two or three cycles. Certain instructions that involve skipping over the subsequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or double word instruction. Moreover, double word moves require two cycles. The double word instructions execute in two instruction cycles. Note: For more details on the instruction set, refer to the “dsPIC30F/33F Programmer’s Reference Manual” (DS70157). © 2008 Microchip Technology Inc. Preliminary DS70293B-page 263
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