Synchrophasor Initiative in India - erldc
Synchrophasor Initiative in India - erldc
Synchrophasor Initiative in India - erldc
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SYNCHROPHASORS - INITIATIVE IN INDIA JUNE 20125.1.4 Case Study-9: Tripp<strong>in</strong>g at 400kV Muradnagar & Moradabad on 29-May-2011Voltage profile at 400kV Kanpur Bus dur<strong>in</strong>g <strong>in</strong>cident of multiple tripp<strong>in</strong>g at 400kV Muradnagarand Moradabad Substations is shown <strong>in</strong> the figure 52. It can be observed that there is delayedfault clearance i.e., <strong>in</strong> 520 milli seconds which is much beyond the fault clear<strong>in</strong>g time asmandated <strong>in</strong> the <strong>India</strong>n Electricity Grid Code (IEGC). This <strong>in</strong>dicates the clear<strong>in</strong>g of fault <strong>in</strong> Zone-2 time of distance protection. The same was validated based on field <strong>in</strong>formation.Figure 52: Detection of delayed fault clearancePOSOCO Page 65 of 143