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Programmer’s Reference for the VE RTSMsmotherboard.vfs2.parameter=valueTable 3-14 VFS2 configuration parametersParameter Description Type Values DefaultmountPath to host folder to make accessibleinside the model.string Valid path [emptystring]Visualization parametersTable 3-15 lists the visualization instantiation-time parameters that you can change when themodel is started.The syntax to use in a configuration file or on the command line is:motherboard.vis.parameter=valueTable 3-15 Visualization configuration parametersParameter Description Type Values Defaulttrap_keyTrap key that works with Left Ctrl totoggle mouse display.integer - 0x6Brate_limit-enable Rate limit simulation boolean true or false truedisable_visualizationDisable the VEVisualisation componenton model startupboolean true or false falseFor more information on the visualization component, see the Fast Models Reference Manual.3.2.3 RTSM_VE_Cortex-A15MPx1, RTSM_VE_Cortex-A15MPx2 and RTSM_VE_Cortex-A15MPx4coretile parametersTable 3-16 lists the Cortex-A15 multiprocessor coretile parameters that you can change whenyou start the RTSM_VE_Cortex-A15MPx1, RTSM_VE_Cortex-A15MPx2 orRTSM_VE_Cortex-A15MPx4 models. All listed parameters are instantiation-time parameters.This coretile RTSM is based on r0p0beta of the Cortex-A15 processor.The syntax to use in a configuration file is:cluster.parameter=valueTable 3-16 RTSM_VE_Cortex-A15MPxn coretile parametersParameter Description TypeAllowedValueDefaultValueCFGSDISABLEDisable some accesses to DICregisters.boolean true or false falseCLUSTER_ID CPU cluster ID value. integer 0-15 0device-accurate-tlbSet whether device-accuratenumber of TLBs are modelledboolean true or false false adic-spi_countNumber of shared peripheralinterrupts implemented.integer0-224, inincrements of3264ARM DUI 0575A Copyright © 2011 ARM. All rights reserved. 3-10ID051811Non-Confidential
Programmer’s Reference for the VE RTSMsTable 3-16 RTSM_VE_Cortex-A15MPxn coretile parameters (continued)Parameter Description TypeAllowedValueDefaultValueIMINLNl1_dcache-state_modelledl1_icache-state_modelledInstruction cache minimum linesize: false=32 bytes, true=64bytesSet whether L1 D-cache hasstateful implementationSet whether L1 I-cache hasstateful implementationboolean true or false trueboolean true or false falseboolean true or false falsel2_cache-size Set L2 cache size in bytes integer 0x080000,0x100000,0x200000,0x400000.0x400000l2_cache-state_modelledSet whether L2 cache hasstateful implementationboolean true or false falsea. Specifying false enables modeling a different number of TLBs if this improves simulation performance. Thesimulation is architecturally accurate, but not device accurate. Architectural accuracy is almost alwayssufficient. Specify true if device accuracy is required.The RTSM_VE_Cortex-A15MPx1 has the PERIPHBASE parameter set to 0x1F000000, whichis the base address of peripheral memory space on VE hardware.Table 3-17 provides a description of the configuration parameters for each Cortex-A15MP core.These parameters are set individually for each Cortex-A15 core you have in your system. Eachcore has its own timer and watchdog.The syntax to use in a configuration file is:cluster.cpun.parameter=valuewhere n is the CPU number, from 0 to 3 inclusive.Table 3-17 RTSM_VE_Cortex-A15MPxn coretile parameters - individual coresParameter Description TypeAllowedValueDefaultValueCFGENDCP15SDISABLETEINITVINITHIase-present aInitialize to BE8endianness.Initialize to disable accessto some CP15 registers.Thumb exception enable.The default has exceptionsincluding reset handled inARM state.Initialize with high vectorsenabled.Set whether processormodel has been built withNEON support.boolean true or false falseboolean true or false falseboolean true or false falseboolean true or false falseboolean true or false trueARM DUI 0575A Copyright © 2011 ARM. All rights reserved. 3-11ID051811Non-Confidential
Page 1 and 2: Real-Time System ModelVersion 1.0Re
Page 3 and 4: ContentsReal-Time System Model Refe
Page 5 and 6: PrefaceThis preface introduces the
Page 7 and 8: Prefaceboldmonospacemonospacemonosp
Page 9 and 10: PrefaceFeedbackARM welcomes feedbac
Page 11 and 12: Introduction1.1 Introduction to sys
Page 13 and 14: Introduction• ARMv7A-AEM on page
Page 15 and 16: IntroductionA complete model implem
Page 17 and 18: Getting Started with Real-Time Syst
Page 33 and 34: Chapter 3Programmer’s Reference f
Page 35 and 36: Programmer’s Reference for the VE
Page 41: Programmer’s Reference for the VE
Page 61 and 62: Programmer’s Reference for the MP
Page 69 and 70: GlossaryThis glossary lists abbrevi
Page 71: GlossaryVEVersatile Express. A hard

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