PDF version - ARM Information Center

Programmer’s Reference for the VE RTSMsTable 3-19 RTSM_VE_CortexR5_MPxn coretile parameters (continued)Parameter Description Type Allowed ValueDefaultValueNUM_WATCHPOINTSdcache-state_modelledicache-state_modelledControls with how manywatchpoint pairs the modelhas been configured. Thisonly affects the buildoptions registers, becausedebug is not modeled.Set whether D-cache hasstateful implementation.Set whether I-cache hasstateful implementation.Integer 1-8 2Boolean true/false falseBoolean true/false falseTable 3-20 provides a description of the configuration parameters for eachRTSM_VE_Cortex-R5_MPx1 component processor. These parameters are set individually foreach processor you have in your system.Table 3-20 RTSM_VE_CortexR5_MPxn coretile parameters - individual coresParameter Description Type Allowed ValueDefaultValueCFGATCMSZ Sets the size of the ATCM. Integer 0x00000000 - 0xE 0xECFGBTCMSZ Sets the size of the BTCM. Integer 0x00000000 - 0xE 0xECFGENDCFGIECFGNMFIInitialize to BE8endianness.Set the reset value of theinstruction endian bit.Enable non-maskable fastinterrupts on startup.Boolean true/false falseBoolean true/false falseBoolean true/false falseDP_FLOATSets whetherdouble-precisioninstructions are available.For more information, seethe ARM ArchitectureReference Manuals.Booleantrue/false.If True, then double precisionVFP is supported.If False, thenthe VFP is single precision only.trueNUM_MPU_REGIONSets the number of MPUregions.Integer 0x00, 0xC, 0x10.0 = no MPU.0xCTEINITVINITHIThumb exception enable.The default has exceptionsincluding reset handled inARM state.Initialize with high vectorsenabled.Boolean true/false falseBoolean true/false falseARM DUI 0575A Copyright © 2011 ARM. All rights reserved. 3-15ID051811Non-Confidential