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Programmer’s Reference for the VE RTSMsNoteIn the view of CPU2, the shared cache block marked L3U$ is at Level 2 in the memory systemhierarchy.Debug architecture configurationThe ARMv7 Debug architecture contains a number of optional features. The parameters listedin Table 3-26 control which of these features are implemented by the model.Table 3-26 Debug architecture configuration parametersParameter Description Defaultimplements_OSSaveAndRestoreDBGOSLOCKINITimplements_secure_user_halting_debugAdd support for the OS Save and Restore mechanismimplemented by DBGOSSRR and other registers.Initial value for the Locked bit in DBGOSLSR. When thisbit is set, software access to debug registers is restricted.Permit debug events in Secure User mode when invasivedebug is not permitted in Secure privileged modes.(Deprecated in ARM v7.)true0x1falseDBGPID Value for CP14 DBGPID registers 0x8000bb000DBGCID Value for CP14 DBGCID registers 0x0DBGDSCCR_mask Implemented bits of DBGDSCCR 0x7cpu[n].DBGDRAR Value for Debug ROM address register 0x0cpu[n].DBGSRAR Value for Debug Self address register 0x0Core configurationThese parameters are repeated in groups cpu0-cpu3 for each core in the processor. SeeTable 3-27.Table 3-27 Core configuration parametersParameter Description Defaultcpu[n].CFGEND0 Starts the core in big endian BE8 mode falsecpu[n].CFGNMFISets the NMFI bit in the System Control Register (SCTLR)that prevents the FIQ interrupt from being masked inAPSR.falsecpu[n].CFGTE Starts the core in Thumb2 mode falsecpu[n].CP15SDISABLE Disables access to some CP15 registers falsecpu[n].VINITHIStarts the core with high vectors enabled, the vector baseaddress is 0xFFFF0000falsecpu[n].implements_neon Support NEON in this CPU truecpu[n].implements_thumbEE Support ThumbEE in this CPU truecpu[n].implements_trustzone Support TrustZone in this CPU trueARM DUI 0575A Copyright © 2011 ARM. All rights reserved. 3-22ID051811Non-Confidential