MPhil thesis of Lo Chi Wa - Department of Electronic & Computer ...

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Fig. 36 Dual-path loop filter principle.............................................................................50Fig. 37 Schematic of the largest resistor implemented by NMOS transistors ....................52Fig. 38 Resistance of NMOS resistor vs. input voltage....................................................53Fig. 39 Schematic of current steering charge-pump.........................................................54Fig. 40 Schematic diagram of the current steering charge-pump (pump-down currentbranch only) and the switch capacitor driving stage.............................................54Fig. 41 Schematic of frequency phase detector................................................................55Fig. 42 Schematic of simplified TSPL D F/F ..................................................................55Fig. 43 Tuning curve by switchable-capacitor-array with gain adjustment of finiteresolution ...........................................................................................................57Fig. 44 gain and offset adjustments for the switchable-capacitor-array control .................58Fig. 45 System diagram of the multi-modulus prescalar ..................................................58Fig. 46 Schematic of high speed divide-by-2,2.5,3,3.5 multi-modulus divider..................59Fig. 47 Timing diagram of the high-speed divide-by-2,2.5,3,3.5 multi-modulus divider ...59Fig. 48 AC couple and biasing for the input of the prescalar............................................60Fig. 49 Schematic diagram of the high speed divide-by-2 divider ....................................60Fig. 50 Schematic diagram of the high speed D latch ......................................................61Fig. 51 Schematic of the phase select circuit ...................................................................61Fig. 52 Schematic of the pseudo-NMOS a) inverter, b) OR gate, c) wired-AND gate.......62Fig. 53 Schematic diagram of the dual-modulus divider ..................................................62Fig. 54 Schematic diagram of the TSP D F/F with AND gate embedded..........................63Fig. 55 Schematic diagram of the low speed divide-by-two divider.................................63Fig. 56 Schematic diagram of the TSP D F/F ..................................................................64Fig. 57 Schematic diagram of the state machine of the phase select .................................65Fig. 58 Schematic diagram of the static D latch...............................................................65Fig. 59 System diagram of MESH-3 Sigma-Delta modulator ..........................................68Fig. 60 Schematic of the accumulator .............................................................................69Fig. 61 Evolution of the digital accumulator a) System diagram of a digital adder b-d)Different views of system diagram of a digital accumulator.................................69Fig. 62 Schematic of the 3-order digital Sigma-Delta modulator with a dither input .........70Fig. 63 System and schematic diagrams of the quantization noise cancellation.................71Fig. 64 Output of a first-order modulator with a half-range input.....................................72Fig. 65 Output spectrums of a sigma-delta modulator a) random input b) DC or periodicinput c) DC or periodic input with dither.............................................................72Fig. 66 Schematic diagram of the pseudo random sequence generator .............................73Fig. 67 Schematic diagram of the 3-order high pass digital filter......................................73Fig. 68 Different methods to generate quadrature outputs................................................75Fig. 69 Schematic of coupled LC oscillators with quadrature outputs ..............................75Fig. 70 (a) Schematic of LC oscillator; (b) Output-input characteristic of gm cell.............77Fig. 71 (a) Less current flow in gm cell when small differential output; (b) More currentflow in gm cell when large differential output .....................................................78Fig. 72 (a) Single-ended output voltage of LC oscillator; (b) Common source voltage;(c) Current flow into gm cell. (1) without capacitor (2) with capacitor..................78Fig. 73 Current flows in two oscillators with 90-degree phase difference .........................79Fig. 74 (a) Output voltage of LC oscillator; (b) Common source voltage; (c) Currentflow into gm cell. (1) without capacitor or common source node connection (2)with capacitor (3) with connection ......................................................................80Fig. 75 Another view of a matched coupled-LC oscillators..............................................81vii
Fig. 76 Amplitudes and currents of the two mistmatched oscillators : T1: period whendifferential output is large in oscillator A; T2: period when differential output islarge in oscillator B ............................................................................................81Fig. 77 IQ outputs of coupled LC oscillators (a) without common source connection and(b) with connection.............................................................................................82Fig. 78 Circuit to verify imperfect control of the phase for different IQ amplitudes ..........82Fig. 79 Output voltage waveform of two LC oscillators with common source nodeconnection only ..................................................................................................83Fig. 80 Phase error with time of coupled LC oscillators without common sourceconnection and with connection ..........................................................................84Fig. 81 Different views of the coupled-LC oscillators......................................................85Fig. 82 Floorplan of the Gm cell transistors (matched pairs in dotted rectangles) and thecorresponding schematic.....................................................................................86Fig. 83 a) Floorplan of four inductors with rotational symmetry b) Floorplan of the twopairs of inductors in the two oscillators with x-symmetry.....................................87Fig. 84 Layouts of oscillators a) four inductors with rotational symmetry b) two pairs ofinductors in the two oscillators with x-symmetry.................................................87Fig. 85 Other alternative arrangement of inductors and the corresponding layout.............88Fig. 86 a) Amplitude mismatch with mismatch error in varactors; b) phase mismatchwith mismatch error in varactors.........................................................................89Fig. 87 Layout of switchable-capacitor-array ..................................................................91Fig. 88 Layout of half of the whole switchable-capacitor array ........................................92Fig. 89 Layout of P+ Nwell varactor...............................................................................93Fig. 90 Layout of metal-2 layer of the inductor ...............................................................95Fig. 91 Layout of metal-3 layer of the inductor ...............................................................95Fig. 92 Layout of the inductor ........................................................................................96Fig. 93 Zoomed view of the interconnection of two layers of the inductor .......................96Fig. 94 Layout of the voltage-controlled oscillator ..........................................................98Fig. 95 Schematic of the voltage-controlled oscillator .....................................................98Fig. 96 Layout of the frequency synthesizer.................................................................. 100Fig. 97 Block diagram of the frequency synthesizer ...................................................... 100Fig. 98 Die photo of the frequency synthesizer and the test structures............................ 101Fig. 99 Testing setup for the passive component measurement ...................................... 103Fig. 100 Capacitance of the testing pads of the passive components vs. frequency ......... 104Fig. 101 Resistance of the testing pads of the passive components vs. frequency............ 105Fig. 102 Quality factor of the testing pads of the passive components vs. frequency....... 105Fig. 103 Testing structure of the spiral inductor ............................................................ 106Fig. 104 Inductance of the inductor vs. frequency ......................................................... 106Fig. 105 Series resistance of the inductor vs. frequency................................................. 107Fig. 106 Quality factor of the inductor vs. frequency..................................................... 107Fig. 107 One-port S-parameter of the inductor and the corresponding fitting curve ........ 108Fig. 108 Narrow band model of the spiral inductor........................................................ 108Fig. 109 Testing structure of the varactor...................................................................... 109Fig. 110 Capacitance of the varactor vs. bias................................................................. 110Fig. 111 Series resistance of the varactor vs. bias .......................................................... 110Fig. 112 Quality factor of the varactor vs. bias .............................................................. 110Fig. 113 Testing structure of the N-well substrate parasitic diode .................................. 111Fig. 114 Capacitance of the N-well substrate parasitic diode vs. bias ............................. 112Fig. 115 Series resistance of the N-well substrate parasitic diode vs. bias....................... 112viii
Page 1 and 2: A 1.5-V 900-Mhz Monolithic CMOSFast
Page 3 and 4: A 1.5-V 900-Mhz Monolithic CMOS Fas
Page 5 and 6: Table of ContentsPageAcknowledgment
Page 7 and 8: Testing setup......................
Page 9: List of FiguresPageFig. 1 Block dia
Page 13 and 14: Chapter 1 IntroductionBackgroundWir
Page 15 and 16: applications because it can provide
Page 17 and 18: existing monolithic frequency synth
Page 19 and 20: the receiver frequency band is from
Page 21 and 22: out-of-bandin-bandout-of-band0dBmin
Page 23 and 24: Based on the maximum interference,
Page 25 and 26: carrierdBcspur∆fFig. 8 Frequency
Page 27 and 28: Spurs requirement (dBc)Frequency of
Page 29 and 30: The frequency diversity can be perf
Page 31 and 32: Chapter 3 System DesignPhase-locked
Page 33 and 34: coarse tuning can be provided by th
Page 35 and 36: array is now possible. Moreover, th
Page 37 and 38: performance of the synthesizer 9 .
Page 39 and 40: signalquantizationnoisea) f b)signa
Page 41 and 42: esolution. The loop bandwidth is 80
Page 43 and 44: the output value between 0 and 0.5,
Page 45 and 46: The coupled-LC oscillators can be v
Page 47 and 48: 890MHzf25MHz243KHz865MHzFig. 23 Tun
Page 49 and 50: onoffCwellClinearCwellClinearCwellC
Page 51 and 52: spirals of similar sizes is around
Page 53 and 54: in Fig. 27a and Fig. 27b, the same
Page 55 and 56: conductance (Gm) and the reciprocal
Page 57 and 58: −19⎛ 900M⎞0.0259×1.6×10 ×
Page 59 and 60: GdoVinFig. 32 Gdo of the proposed L
Page 61 and 62:
RzCzIcpCpR4C4a)IcpCzR4B.IcpCpRpC4b)
Page 63 and 64:
Usually, capacitors in the filter o
Page 65 and 66:
RVinFig. 38 Resistance of NMOS resi
Page 67 and 68:
feedback path to prevent the proble
Page 69 and 70:
890MHz25MHz865MHzfA+∆A
Page 71 and 72:
High-speed multi-modulus dividerThe
Page 73 and 74:
CLKQBQDDBFig. 50 Schematic diagram
Page 75 and 76:
ANDgateABclkclkclkclkQBFig. 54 Sche
Page 77 and 78:
f o/2 /2,3 /2,3 /2 /2f div/4Combina
Page 79 and 80:
next stage, as shown in the Fig. 59
Page 81 and 82:
co10bDclkclkFig. 60 Schematic of th
Page 83 and 84:
(1-Z -1 ) 23bDQBclkZ -1 (1-Z -1 )2b
Page 85 and 86:
X 16clkDclkQBDclkQBFig. 66 Schemati
Page 87 and 88:
~90 oa) b) c)Fig. 68 Different meth
Page 89 and 90:
(dotted line). As the oscillation c
Page 91 and 92:
In practice, it is not desirable to
Page 93 and 94:
and decrease in amplitude mismatch
Page 95 and 96:
Current interactionThe two oscillat
Page 97 and 98:
equirements. Fortunately, by connec
Page 99 and 100:
LC oscillators are put apart to red
Page 101 and 102:
Gain mismatch (in %)Two oscillators
Page 103 and 104:
equals to1 . By doubling the height
Page 105 and 106:
30 is obtained. It is because the s
Page 107 and 108:
The spiral inductor is designed and
Page 109 and 110:
oscillators (shown in the upper and
Page 111 and 112:
Synthesizer LayoutThe layout and th
Page 113 and 114:
Die LayoutFig. 98 shows the die pho
Page 115 and 116:
Testing setupThe testing setup show
Page 117 and 118:
Resistance (ohms)Freq (Hz)Fig. 101
Page 119 and 120:
Resistance (ohms)Freq (Hz)Fig. 105
Page 121 and 122:
VaractorFig. 109 shows the testing
Page 123 and 124:
Table 5 Summary of parameters of va
Page 125 and 126:
Table 6 Summary of N-well substrate
Page 127 and 128:
Fig. 120 Quality factor of the swit
Page 129 and 130:
The decrease in quality factor is d
Page 131 and 132:
Fig. 126 Schematic diagram of the p
Page 133 and 134:
Output frequency(MHz)Number of swit
Page 135 and 136:
Gain (MHz/V)Tuning voltage (v)Fig.
Page 137 and 138:
on the process variation. Therefore
Page 139 and 140:
voltage (Vos = Rp x Ios) appeared.
Page 141 and 142:
Although the spurs are quite large,
Page 143 and 144:
GMSK signals with 0.3 BT and a bit
Page 145 and 146:
Power spectral density (dB)(b)(a)(c
Page 147 and 148:
Summary of performanceA summary of
Page 149 and 150:
Table 10 Comparison of performances
Page 151 and 152:
As the voltage-controlled oscillato
Page 153 and 154:
Bibliography1 Thomas H. Lee, The De
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MPhil thesis of Lo Chi Wa - Department of Electronic & Computer ...

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