MPhil thesis of Lo Chi Wa - Department of Electronic & Computer ...

Switching speedSwitching speed is limited in PLL based synthesizers. In conventional design, the finestfrequency resolution equals to the reference frequency. However, in order to fulfill therequirement of stability, the larger loop bandwidth is limited to approximately 1/10 ofthe reference frequency 1 . As a result, PLL synthesizers with a fine frequency resolutionhave a small loop bandwidth and thus a low switching speed. Moreover, at differentoutput frequencies, the varactor of the VCO is biased with different voltages and hasdifferent gains. The loop gain is therefore not constant through out the whole outputfrequency range. In some frequency range, the loop bandwidth and speed are smallerthan the optimum because the stability of the loop has to be ensured in all cases.Although some linearization techniques can be used 2 , they require the characteristic of apre-measured varactor and thus can only provide limited linearization.Supply voltageTo compensate the center frequency variation in voltage controlled oscillator, a largetuning range is required. In this case, large voltage range is required to bias the varactorfor large frequency range. Thus, large supply voltage is needed.MonolithicTo meet the tough phase noise specification, huge capacitors are needed to reduce thethermal noise in the charge-pump and loop filter. The capacitors are usually so largethat they will either occupy a very large chip area or have to be put off-chip.Thesis overviewIn this work, we will try to solve the problems mentioned above including substratenoise, frequency switching speed, supply voltage and chip area, which are faced by4