MPhil thesis of Lo Chi Wa - Department of Electronic & Computer ...

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Chapter 2 SpecificationsFrequency range and resolutionIn a wireless receiver, as shown in Fig. 1, the radio-frequency (RF) signal is receivedthrough the antenna and amplified by the low-noise amplifier (LNA). Since the outputfrequency of the down-convert mixer is the absolute value of the difference of the twoinput frequencies, both the desired signal RF and the image signal RF-2IF can be mixeddown to IF. Therefore RF signal is filtered by the RF image-rejection filter in order toremove the RF-2IF signal before it is down-converted as shown in Fig. 2. As the mixerperforms the frequency subtraction, resultant signal of the mixer RF-LO which equalsto the intermediate-frequency (IF) will pass through the channel selection filter. Onlythe desired channel is remained and sampled by the analog-to-digital converter.RFIFLOFig. 1 Block diagram of a receiverAs shown in Fig. 3, the mixer will mix down the desired channel within receiverfrequency band (935MHz – 960MHz) to exactly 70MHz and let the IF channelselection filter which is centered at 70MHz to filter out all other unwanted channels. As6
the receiver frequency band is from 935MHz to 960MHz and the IF is 70MHz, theoutput frequency range of the frequency synthesizer will be from 865MHz to 890MHz.The channel spacing in the receiver band is 200kHz and therefore the frequencyresolution of the frequency synthesizer is 200kHz.Down-conversionImage-rejection filterIFImagesignalRF-2IFLODesiredsignalRFfreqIFIFFig. 2 Frequency domain representation of the down-conversion and the relationship between RF,image, LO, and IF signalsDown-conversionIFRFChannel-selection filterDesiredchannelfreqFig. 3 Frequency domain representation of the channel selection7
Page 1 and 2: A 1.5-V 900-Mhz Monolithic CMOSFast
Page 3 and 4: A 1.5-V 900-Mhz Monolithic CMOS Fas
Page 5 and 6: Table of ContentsPageAcknowledgment
Page 7 and 8: Testing setup......................
Page 9 and 10: List of FiguresPageFig. 1 Block dia
Page 11 and 12: Fig. 76 Amplitudes and currents of
Page 13 and 14: Chapter 1 IntroductionBackgroundWir
Page 15 and 16: applications because it can provide
Page 17: existing monolithic frequency synth
Page 21 and 22: out-of-bandin-bandout-of-band0dBmin
Page 23 and 24: Based on the maximum interference,
Page 25 and 26: carrierdBcspur∆fFig. 8 Frequency
Page 27 and 28: Spurs requirement (dBc)Frequency of
Page 29 and 30: The frequency diversity can be perf
Page 31 and 32: Chapter 3 System DesignPhase-locked
Page 33 and 34: coarse tuning can be provided by th
Page 35 and 36: array is now possible. Moreover, th
Page 37 and 38: performance of the synthesizer 9 .
Page 39 and 40: signalquantizationnoisea) f b)signa
Page 41 and 42: esolution. The loop bandwidth is 80
Page 43 and 44: the output value between 0 and 0.5,
Page 45 and 46: The coupled-LC oscillators can be v
Page 47 and 48: 890MHzf25MHz243KHz865MHzFig. 23 Tun
Page 49 and 50: onoffCwellClinearCwellClinearCwellC
Page 51 and 52: spirals of similar sizes is around
Page 53 and 54: in Fig. 27a and Fig. 27b, the same
Page 55 and 56: conductance (Gm) and the reciprocal
Page 57 and 58: −19⎛ 900M⎞0.0259×1.6×10 ×
Page 59 and 60: GdoVinFig. 32 Gdo of the proposed L
Page 61 and 62: RzCzIcpCpR4C4a)IcpCzR4B.IcpCpRpC4b)
Page 63 and 64: Usually, capacitors in the filter o
Page 65 and 66: RVinFig. 38 Resistance of NMOS resi
Page 67 and 68: feedback path to prevent the proble
Page 69 and 70:
890MHz25MHz865MHzfA+∆A
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High-speed multi-modulus dividerThe
Page 73 and 74:
CLKQBQDDBFig. 50 Schematic diagram
Page 75 and 76:
ANDgateABclkclkclkclkQBFig. 54 Sche
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f o/2 /2,3 /2,3 /2 /2f div/4Combina
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next stage, as shown in the Fig. 59
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co10bDclkclkFig. 60 Schematic of th
Page 83 and 84:
(1-Z -1 ) 23bDQBclkZ -1 (1-Z -1 )2b
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X 16clkDclkQBDclkQBFig. 66 Schemati
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~90 oa) b) c)Fig. 68 Different meth
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(dotted line). As the oscillation c
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In practice, it is not desirable to
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and decrease in amplitude mismatch
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Current interactionThe two oscillat
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equirements. Fortunately, by connec
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LC oscillators are put apart to red
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Gain mismatch (in %)Two oscillators
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equals to1 . By doubling the height
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30 is obtained. It is because the s
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The spiral inductor is designed and
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oscillators (shown in the upper and
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Synthesizer LayoutThe layout and th
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Die LayoutFig. 98 shows the die pho
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Testing setupThe testing setup show
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Resistance (ohms)Freq (Hz)Fig. 101
Page 119 and 120:
Resistance (ohms)Freq (Hz)Fig. 105
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VaractorFig. 109 shows the testing
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Table 5 Summary of parameters of va
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Table 6 Summary of N-well substrate
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Fig. 120 Quality factor of the swit
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The decrease in quality factor is d
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Fig. 126 Schematic diagram of the p
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Output frequency(MHz)Number of swit
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Gain (MHz/V)Tuning voltage (v)Fig.
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on the process variation. Therefore
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voltage (Vos = Rp x Ios) appeared.
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Although the spurs are quite large,
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GMSK signals with 0.3 BT and a bit
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Power spectral density (dB)(b)(a)(c
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Summary of performanceA summary of
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Table 10 Comparison of performances
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As the voltage-controlled oscillato
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Bibliography1 Thomas H. Lee, The De
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MPhil thesis of Lo Chi Wa - Department of Electronic & Computer ...

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