MPhil thesis of Lo Chi Wa - Department of Electronic & Computer ...

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819.2MHz to 25.6MHz x 39.5 = 1011.2MHz and the minimal frequency resolution is25.6MHz x 0.5 = 12.8MHz. The 16 division ratios are controlled by a 4-bit digitalsignal. In order to generate the channels with a 200-kHz spacing, a digital sigma-deltamodulator of at least 6 bits is needed because 12.8MHz / 2 6 = 200kHz. Each leastsignificant bit of the 6-bit sigma-delta modulator represents a 0.5 / 2 6 in the divisionratio of the prescalar. Including the four bits to directly control the prescalar, a 10-bitchannel selection word is required to control the output frequency.fin25.6MHzFPD &CP4MSB 32,32.5…39.5LPF32,32.5 .. 39.54b3b 0-0.5Sigma-DeltaModulatorKv=9,1MHz/Vavailable range=9MHzVtune variation=0.1VVCO6.6nH-Rfo865-890,890-915MHzfor LO of RXand DirectModulation of TX8bit Linear Capfreq step=800kHz, ~4 channelsfreq range=250MHz, 750-1000MHz)Channelselection10b6lsb7LSB4bditherGain & offsetadjustmentscoefficientsFig. 20 Detailed system diagram of this designExtra four bits added in the sigma-delta modulator are for the dither signal to randomthe input of the sigma-delta modulator in order to prevent the problem of pattern noiseat the output of the sigma-delta modulator.In a higher-order digital modulator, the output signal swing is larger than the availableoutput value (it will be discussed more in Chapter 4). For a third-order modulator with30
the output value between 0 and 0.5, the signal swing can be up to –1 and 2. Due to theextra signal swing required, the available division ratios will be reduced. As a result,this prescalar with extra division ratios is used. The minimum and maximum divisionratios with this prescalar will become 32-(-1)=33 and 39.5-2+0.5=38 which correspondsto the output frequency 25.6MHz x 33 = 844.8MHz and 972.8MHz. The availableoutput frequency range can still cover the required frequency range (865-915MHz) inboth receiver and transmitter systems.The lower seven bits of the channel selection word represents the 125 channels. Theseseven bits are used to control the switchable-capacitor array to obtain the correct outputfrequency. Since these seven bits only represent the channel number but not the exactfrequency of the channel, a frequency offset is added to obtain the correct frequency forthe channels. Moreover, the frequency change due to a change in the least significant bitin the switchable-capacitor array does not represent exactly a channel. A gainadjustment is required to relate the channel number and the corresponding number ofthe switchable capacitors.A 8-bit switchable-capacitor array is used to provide around 300-MHz tuning range(from 800MHz to 1100MHz) and 800-kHz frequency step. The varactors in the voltagecontrolledoscillator can provide about 9MHz/V. As a result, the tuning voltage of thevaractors will vary within 0.1V.31
Page 1 and 2: A 1.5-V 900-Mhz Monolithic CMOSFast
Page 3 and 4: A 1.5-V 900-Mhz Monolithic CMOS Fas
Page 5 and 6: Table of ContentsPageAcknowledgment
Page 7 and 8: Testing setup......................
Page 9 and 10: List of FiguresPageFig. 1 Block dia
Page 11 and 12: Fig. 76 Amplitudes and currents of
Page 13 and 14: Chapter 1 IntroductionBackgroundWir
Page 15 and 16: applications because it can provide
Page 17 and 18: existing monolithic frequency synth
Page 19 and 20: the receiver frequency band is from
Page 21 and 22: out-of-bandin-bandout-of-band0dBmin
Page 23 and 24: Based on the maximum interference,
Page 25 and 26: carrierdBcspur∆fFig. 8 Frequency
Page 27 and 28: Spurs requirement (dBc)Frequency of
Page 29 and 30: The frequency diversity can be perf
Page 31 and 32: Chapter 3 System DesignPhase-locked
Page 33 and 34: coarse tuning can be provided by th
Page 35 and 36: array is now possible. Moreover, th
Page 37 and 38: performance of the synthesizer 9 .
Page 39 and 40: signalquantizationnoisea) f b)signa
Page 41: esolution. The loop bandwidth is 80
Page 45 and 46: The coupled-LC oscillators can be v
Page 47 and 48: 890MHzf25MHz243KHz865MHzFig. 23 Tun
Page 49 and 50: onoffCwellClinearCwellClinearCwellC
Page 51 and 52: spirals of similar sizes is around
Page 53 and 54: in Fig. 27a and Fig. 27b, the same
Page 55 and 56: conductance (Gm) and the reciprocal
Page 57 and 58: −19⎛ 900M⎞0.0259×1.6×10 ×
Page 59 and 60: GdoVinFig. 32 Gdo of the proposed L
Page 61 and 62: RzCzIcpCpR4C4a)IcpCzR4B.IcpCpRpC4b)
Page 63 and 64: Usually, capacitors in the filter o
Page 65 and 66: RVinFig. 38 Resistance of NMOS resi
Page 67 and 68: feedback path to prevent the proble
Page 69 and 70: 890MHz25MHz865MHzfA+∆A
Page 71 and 72: High-speed multi-modulus dividerThe
Page 73 and 74: CLKQBQDDBFig. 50 Schematic diagram
Page 75 and 76: ANDgateABclkclkclkclkQBFig. 54 Sche
Page 77 and 78: f o/2 /2,3 /2,3 /2 /2f div/4Combina
Page 79 and 80: next stage, as shown in the Fig. 59
Page 81 and 82: co10bDclkclkFig. 60 Schematic of th
Page 83 and 84: (1-Z -1 ) 23bDQBclkZ -1 (1-Z -1 )2b
Page 85 and 86: X 16clkDclkQBDclkQBFig. 66 Schemati
Page 87 and 88: ~90 oa) b) c)Fig. 68 Different meth
Page 89 and 90: (dotted line). As the oscillation c
Page 91 and 92: In practice, it is not desirable to
Page 93 and 94:
and decrease in amplitude mismatch
Page 95 and 96:
Current interactionThe two oscillat
Page 97 and 98:
equirements. Fortunately, by connec
Page 99 and 100:
LC oscillators are put apart to red
Page 101 and 102:
Gain mismatch (in %)Two oscillators
Page 103 and 104:
equals to1 . By doubling the height
Page 105 and 106:
30 is obtained. It is because the s
Page 107 and 108:
The spiral inductor is designed and
Page 109 and 110:
oscillators (shown in the upper and
Page 111 and 112:
Synthesizer LayoutThe layout and th
Page 113 and 114:
Die LayoutFig. 98 shows the die pho
Page 115 and 116:
Testing setupThe testing setup show
Page 117 and 118:
Resistance (ohms)Freq (Hz)Fig. 101
Page 119 and 120:
Resistance (ohms)Freq (Hz)Fig. 105
Page 121 and 122:
VaractorFig. 109 shows the testing
Page 123 and 124:
Table 5 Summary of parameters of va
Page 125 and 126:
Table 6 Summary of N-well substrate
Page 127 and 128:
Fig. 120 Quality factor of the swit
Page 129 and 130:
The decrease in quality factor is d
Page 131 and 132:
Fig. 126 Schematic diagram of the p
Page 133 and 134:
Output frequency(MHz)Number of swit
Page 135 and 136:
Gain (MHz/V)Tuning voltage (v)Fig.
Page 137 and 138:
on the process variation. Therefore
Page 139 and 140:
voltage (Vos = Rp x Ios) appeared.
Page 141 and 142:
Although the spurs are quite large,
Page 143 and 144:
GMSK signals with 0.3 BT and a bit
Page 145 and 146:
Power spectral density (dB)(b)(a)(c
Page 147 and 148:
Summary of performanceA summary of
Page 149 and 150:
Table 10 Comparison of performances
Page 151 and 152:
As the voltage-controlled oscillato
Page 153 and 154:
Bibliography1 Thomas H. Lee, The De
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MPhil thesis of Lo Chi Wa - Department of Electronic & Computer ...

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