MPhil thesis of Lo Chi Wa - Department of Electronic & Computer ...

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A 1.5-V 900-Mhz Monolithic CMOS Fast-Switching FrequencySynthesizer for Wireless ApplicationsbyLo Chi WaApproved by:Dr. Howard Cam LUONGThesis SupervisorDr. Bertram Emil ShiThesis Examination Committee Member (Chairman)Dr. Philip Mok Kwok TaiThesis Examination Committee MemberProf. Philip Ching-Ho ChanHead of Department of Electrical and Electronic EngineeringDepartment of Electrical and Electronic EngineeringThe Hong Kong University of Science and TechnologyJanuary, 2000
A 1.5-V 900-Mhz Monolithic CMOS Fast-Switching FrequencySynthesizer for Wireless ApplicationsbyLo Chi WaFor the degree of Master of Philosophy in Electrical and Electronic Engineeringat the Hong Kong University of Science and Technology in January, 2000ABSTRACTIn modern transceiver designs, a frequency synthesizer with good phase-noise performance isvery important because it affects the efficiency of valuable air channel usage and sensitivity ofsmall signals under the presence of large interference. Fast frequency switching is alsorequired in many TDMA systems and frequency-hopping spread-spectrum systems. Otherthan these, low supply voltage, low power consumption and monolithic design are threeimportant features of any modern analog circuits.However, the above requirements are difficult to be achieved in traditional frequencysynthesizer designs. To solve these problems, a new design of phase-locked loop frequencysynthesizer is proposed. Instead of voltage or current domain, some signals in the phaselockedloop are manipulated in capacitance domain. A binary-weighted switchable-capacitorarray is used to replace the digital-to-analog converter while two varactors connected inparallel replace the voltage adder. This design provides many advantages, includingsimplified analog circuitry, low supply voltage, low power consumption, small chip area, fastfrequency switching and high immunity of substrate noise.A prototype of a 1.5-V 900-Mhz monolithic CMOS fast-switching frequency synthesizerbased on GSM specifications is designed and fabricated to demonstrate the idea. It consumes30mW. The total chip area is 0.9 x 1.1 mm 2 . The settling time is within 150us and phase noiseis –118dBc/Hz at 600kHz offset. The ability of direct-digital modulation is also provided withthe sigma-delta fractional-N architecture.
Page 1: A 1.5-V 900-Mhz Monolithic CMOSFast
Page 5 and 6: Table of ContentsPageAcknowledgment
Page 7 and 8: Testing setup......................
Page 9 and 10: List of FiguresPageFig. 1 Block dia
Page 11 and 12: Fig. 76 Amplitudes and currents of
Page 13 and 14: Chapter 1 IntroductionBackgroundWir
Page 15 and 16: applications because it can provide
Page 17 and 18: existing monolithic frequency synth
Page 19 and 20: the receiver frequency band is from
Page 21 and 22: out-of-bandin-bandout-of-band0dBmin
Page 23 and 24: Based on the maximum interference,
Page 25 and 26: carrierdBcspur∆fFig. 8 Frequency
Page 27 and 28: Spurs requirement (dBc)Frequency of
Page 29 and 30: The frequency diversity can be perf
Page 31 and 32: Chapter 3 System DesignPhase-locked
Page 33 and 34: coarse tuning can be provided by th
Page 35 and 36: array is now possible. Moreover, th
Page 37 and 38: performance of the synthesizer 9 .
Page 39 and 40: signalquantizationnoisea) f b)signa
Page 41 and 42: esolution. The loop bandwidth is 80
Page 43 and 44: the output value between 0 and 0.5,
Page 45 and 46: The coupled-LC oscillators can be v
Page 47 and 48: 890MHzf25MHz243KHz865MHzFig. 23 Tun
Page 49 and 50: onoffCwellClinearCwellClinearCwellC
Page 51 and 52: spirals of similar sizes is around
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in Fig. 27a and Fig. 27b, the same
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conductance (Gm) and the reciprocal
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−19⎛ 900M⎞0.0259×1.6×10 ×
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GdoVinFig. 32 Gdo of the proposed L
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RzCzIcpCpR4C4a)IcpCzR4B.IcpCpRpC4b)
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Usually, capacitors in the filter o
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RVinFig. 38 Resistance of NMOS resi
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feedback path to prevent the proble
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890MHz25MHz865MHzfA+∆A
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High-speed multi-modulus dividerThe
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CLKQBQDDBFig. 50 Schematic diagram
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ANDgateABclkclkclkclkQBFig. 54 Sche
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f o/2 /2,3 /2,3 /2 /2f div/4Combina
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next stage, as shown in the Fig. 59
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co10bDclkclkFig. 60 Schematic of th
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(1-Z -1 ) 23bDQBclkZ -1 (1-Z -1 )2b
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X 16clkDclkQBDclkQBFig. 66 Schemati
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~90 oa) b) c)Fig. 68 Different meth
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(dotted line). As the oscillation c
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In practice, it is not desirable to
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and decrease in amplitude mismatch
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Current interactionThe two oscillat
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equirements. Fortunately, by connec
Page 99 and 100:
LC oscillators are put apart to red
Page 101 and 102:
Gain mismatch (in %)Two oscillators
Page 103 and 104:
equals to1 . By doubling the height
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30 is obtained. It is because the s
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The spiral inductor is designed and
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oscillators (shown in the upper and
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Synthesizer LayoutThe layout and th
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Die LayoutFig. 98 shows the die pho
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Testing setupThe testing setup show
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Resistance (ohms)Freq (Hz)Fig. 101
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Resistance (ohms)Freq (Hz)Fig. 105
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VaractorFig. 109 shows the testing
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Table 5 Summary of parameters of va
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Table 6 Summary of N-well substrate
Page 127 and 128:
Fig. 120 Quality factor of the swit
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The decrease in quality factor is d
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Fig. 126 Schematic diagram of the p
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Output frequency(MHz)Number of swit
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Gain (MHz/V)Tuning voltage (v)Fig.
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on the process variation. Therefore
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voltage (Vos = Rp x Ios) appeared.
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Although the spurs are quite large,
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GMSK signals with 0.3 BT and a bit
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Power spectral density (dB)(b)(a)(c
Page 147 and 148:
Summary of performanceA summary of
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Table 10 Comparison of performances
Page 151 and 152:
As the voltage-controlled oscillato
Page 153 and 154:
Bibliography1 Thomas H. Lee, The De
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