MPhil thesis of Lo Chi Wa - Department of Electronic & Computer ...

next stage, as shown in the Fig. 59. The outputs of the three stages will pass throughsome filters and be added together. For the three stages, their outputs will be thedelayed version of their input and first-order high-pass quantization noise. For the inputx, the outputs of the three stages are as the following:y= z -1 x+(1-z -1 )e (first stage)y’= z -1 e+(1-z -1 )e’(second stage)y’’= z -1 e+ z -1 (1-z -1 )e’+(1-z -1 )e’’ (three stage)By adding the filtered outputs of the three stages,z -2 y+ z -1 (1- z -1 )y’+(1- z -1 ) 2 y’’= z -3 x+(1- z -1 ) 3 e’’All of the quantization noise except the third-order high-pass filtered noise from thethird stage will be cancelled. The final output will be the delayed version of the input xand the third-order high-pass quantization noise.To implement the required first-order sigma-delta modulator, a digital adder and a D-type flip-flip can be used. The digital adder and the flip-flop form a digital accumulator,as in Fig. 60. The input of the adder is the input of the modulator, the carry-out of theaccumulator is the output, and the accumulated value is the quantization error. Toexplain it, firstly, the digital adder can be modeled as Fig. 61a. It is normally an adder.However, since the adder will be overflow in the sum is too large, it will only provide67