MPhil thesis of Lo Chi Wa - Department of Electronic & Computer ...

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solid line) and the nominal frequency (around 890MHz, dotted line). With 0-1.5Vtuning voltage (or 1.5-0V reverse biased), the corresponding frequency tuning is 756-748MHz, 899-885MHz and 975-957MHz.Output frequency (MHz)Tuning voltage (V)Fig. 130 Frequency vs. tuning voltage of the voltage-controlled oscillatorThe gains of the voltage-controlled oscillator at these three frequency ranges are shownin Fig. 131. At nominal bias condition, the gains are 4MHz/V, 6MHz/V and 7MHz/V at750Mhz (dashed line), 900MHz (solid line) and 970MHz (dotted line). The gainsincrease when the tuning voltage increases. The maximal values 13MHz/V, 23MHz/Vand 33MHz/V are obtained when the tuning voltage is closed to 1.5V. Compared to thedesigned gain at 900MHz (9MHz/V), the measured gain is smaller due to the largercapacitance in the switchable-capacitor array.122
Gain (MHz/V)Tuning voltage (v)Fig. 131 Gain of voltage-controlled oscillator vs. tuning voltageAmplitude and phase matchingsThis voltage-controlled oscillator can provide quadrature outputs for the imagerejectionmixer. The amplitude and phase matchings of the quadrature outputs of theoscillator affect the available image rejection. Since the outputs are at high frequency, itis very difficult to directly measure the phase difference between the quadratureoutputs. Instead of directly measuring the phase, a single-sideband mixer as shown inFig. 132 can be used to measure the amplitude and phase matchings. A low-frequencyquadrature signal is applied to the mixer and up-converted by the quadrature output ofthe voltage-controlled oscillator. The up-converted signal contains the wanted sidebandand the unwanted sideband. Assuming the low-frequency quadrature signal has verygood amplitude and phase matchings, the amplitude difference between the twosidebands can show the mismatches in the quadrature outputs of the voltage-controlledoscillator. The measured amplitude difference between two sidebands is around 30dBwhich corresponds to smaller than 1-degree phase mismatch and 0.1-dB amplitude123
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A 1.5-V 900-Mhz Monolithic CMOSFast
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A 1.5-V 900-Mhz Monolithic CMOS Fas
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Table of ContentsPageAcknowledgment
Page 7 and 8:
Testing setup......................
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List of FiguresPageFig. 1 Block dia
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Fig. 76 Amplitudes and currents of
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Chapter 1 IntroductionBackgroundWir
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applications because it can provide
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existing monolithic frequency synth
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the receiver frequency band is from
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out-of-bandin-bandout-of-band0dBmin
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Based on the maximum interference,
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carrierdBcspur∆fFig. 8 Frequency
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Spurs requirement (dBc)Frequency of
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The frequency diversity can be perf
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Chapter 3 System DesignPhase-locked
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coarse tuning can be provided by th
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array is now possible. Moreover, th
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performance of the synthesizer 9 .
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signalquantizationnoisea) f b)signa
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esolution. The loop bandwidth is 80
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the output value between 0 and 0.5,
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The coupled-LC oscillators can be v
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890MHzf25MHz243KHz865MHzFig. 23 Tun
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onoffCwellClinearCwellClinearCwellC
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spirals of similar sizes is around
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in Fig. 27a and Fig. 27b, the same
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conductance (Gm) and the reciprocal
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−19⎛ 900M⎞0.0259×1.6×10 ×
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GdoVinFig. 32 Gdo of the proposed L
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RzCzIcpCpR4C4a)IcpCzR4B.IcpCpRpC4b)
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Usually, capacitors in the filter o
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RVinFig. 38 Resistance of NMOS resi
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feedback path to prevent the proble
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890MHz25MHz865MHzfA+∆A
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High-speed multi-modulus dividerThe
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CLKQBQDDBFig. 50 Schematic diagram
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ANDgateABclkclkclkclkQBFig. 54 Sche
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f o/2 /2,3 /2,3 /2 /2f div/4Combina
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next stage, as shown in the Fig. 59
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co10bDclkclkFig. 60 Schematic of th
Page 83 and 84: (1-Z -1 ) 23bDQBclkZ -1 (1-Z -1 )2b
Page 85 and 86: X 16clkDclkQBDclkQBFig. 66 Schemati
Page 87 and 88: ~90 oa) b) c)Fig. 68 Different meth
Page 89 and 90: (dotted line). As the oscillation c
Page 91 and 92: In practice, it is not desirable to
Page 93 and 94: and decrease in amplitude mismatch
Page 95 and 96: Current interactionThe two oscillat
Page 97 and 98: equirements. Fortunately, by connec
Page 99 and 100: LC oscillators are put apart to red
Page 101 and 102: Gain mismatch (in %)Two oscillators
Page 103 and 104: equals to1 . By doubling the height
Page 105 and 106: 30 is obtained. It is because the s
Page 107 and 108: The spiral inductor is designed and
Page 109 and 110: oscillators (shown in the upper and
Page 111 and 112: Synthesizer LayoutThe layout and th
Page 113 and 114: Die LayoutFig. 98 shows the die pho
Page 115 and 116: Testing setupThe testing setup show
Page 117 and 118: Resistance (ohms)Freq (Hz)Fig. 101
Page 119 and 120: Resistance (ohms)Freq (Hz)Fig. 105
Page 121 and 122: VaractorFig. 109 shows the testing
Page 123 and 124: Table 5 Summary of parameters of va
Page 125 and 126: Table 6 Summary of N-well substrate
Page 127 and 128: Fig. 120 Quality factor of the swit
Page 129 and 130: The decrease in quality factor is d
Page 131 and 132: Fig. 126 Schematic diagram of the p
Page 133: Output frequency(MHz)Number of swit
Page 137 and 138: on the process variation. Therefore
Page 139 and 140: voltage (Vos = Rp x Ios) appeared.
Page 141 and 142: Although the spurs are quite large,
Page 143 and 144: GMSK signals with 0.3 BT and a bit
Page 145 and 146: Power spectral density (dB)(b)(a)(c
Page 147 and 148: Summary of performanceA summary of
Page 149 and 150: Table 10 Comparison of performances
Page 151 and 152: As the voltage-controlled oscillato
Page 153 and 154: Bibliography1 Thomas H. Lee, The De
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