MPhil thesis of Lo Chi Wa - Department of Electronic & Computer ...

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Chapter 5 Quadrature phase and amplitudematchings in coupled-LC oscillatorsIntroductionAs CMOS technology gets maturer, high performance CMOS monolithic transceiversbecome more and more feasible 17 . In order to get rid of bulky discrete RF filters, imagerejectmixers are employed. One of the challenges is to implement on-chip low-phasenoisevoltage-controlled oscillators with quadrature outputs for LO inputs of imagerejectmixers 1, 18.LC oscillators can satisfy the strict requirements of phase noise, power and outputswing. In order to generate quadrature phase outputs, many methods, as shown in Fig.68, are used, e.g. a) RC-CR network, b) Havens' technique, and c) frequency division,but they suffer from inaccurate phase, amplitude loss, and double frequency operation19. By using two identical LC oscillators with four coupling transistors as shown in Fig.69, even quadrature outputs can be obtained 11 , 20. If the two oscillators are identical, theywill oscillate at the same frequency with quadrature phase difference. However, as themismatches in the two oscillators get larger, the amplitude will be deviated from eachother, and phase difference will be further from 90 degrees. If the mismatch is largeenough, the two oscillators will eventually oscillate independently at differentfrequencies.74
~90 oa) b) c)Fig. 68 Different methods to generate quadrature outputs.A pair of identicalLC oscillatorsCouplingtransistorsFig. 69 Schematic of coupled LC oscillators with quadrature outputsFor LC oscillators, causes of mismatches include geometric error from the process, alarge area of non-uniform substrate under the inductors and varactors, and nearbyobjects, which couple to the tanks both electrically and magnetically. Due to the largearea of the LC resonant tanks, the mismatch problem of the two oscillators will beserious. Although larger coupling transistors with larger bias can force the two nonidenticaloscillations in a more quadrature way, they cannot control the outputamplitudes of the two oscillations and will hurt the phase noise performance as well.75
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A 1.5-V 900-Mhz Monolithic CMOSFast
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A 1.5-V 900-Mhz Monolithic CMOS Fas
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Table of ContentsPageAcknowledgment
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Testing setup......................
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List of FiguresPageFig. 1 Block dia
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Fig. 76 Amplitudes and currents of
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Chapter 1 IntroductionBackgroundWir
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applications because it can provide
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existing monolithic frequency synth
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the receiver frequency band is from
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out-of-bandin-bandout-of-band0dBmin
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Based on the maximum interference,
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carrierdBcspur∆fFig. 8 Frequency
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Spurs requirement (dBc)Frequency of
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The frequency diversity can be perf
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Chapter 3 System DesignPhase-locked
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coarse tuning can be provided by th
Page 35 and 36: array is now possible. Moreover, th
Page 37 and 38: performance of the synthesizer 9 .
Page 39 and 40: signalquantizationnoisea) f b)signa
Page 41 and 42: esolution. The loop bandwidth is 80
Page 43 and 44: the output value between 0 and 0.5,
Page 45 and 46: The coupled-LC oscillators can be v
Page 47 and 48: 890MHzf25MHz243KHz865MHzFig. 23 Tun
Page 49 and 50: onoffCwellClinearCwellClinearCwellC
Page 51 and 52: spirals of similar sizes is around
Page 53 and 54: in Fig. 27a and Fig. 27b, the same
Page 55 and 56: conductance (Gm) and the reciprocal
Page 57 and 58: −19⎛ 900M⎞0.0259×1.6×10 ×
Page 59 and 60: GdoVinFig. 32 Gdo of the proposed L
Page 61 and 62: RzCzIcpCpR4C4a)IcpCzR4B.IcpCpRpC4b)
Page 63 and 64: Usually, capacitors in the filter o
Page 65 and 66: RVinFig. 38 Resistance of NMOS resi
Page 67 and 68: feedback path to prevent the proble
Page 69 and 70: 890MHz25MHz865MHzfA+∆A
Page 71 and 72: High-speed multi-modulus dividerThe
Page 73 and 74: CLKQBQDDBFig. 50 Schematic diagram
Page 75 and 76: ANDgateABclkclkclkclkQBFig. 54 Sche
Page 77 and 78: f o/2 /2,3 /2,3 /2 /2f div/4Combina
Page 79 and 80: next stage, as shown in the Fig. 59
Page 81 and 82: co10bDclkclkFig. 60 Schematic of th
Page 83 and 84: (1-Z -1 ) 23bDQBclkZ -1 (1-Z -1 )2b
Page 85: X 16clkDclkQBDclkQBFig. 66 Schemati
Page 89 and 90: (dotted line). As the oscillation c
Page 91 and 92: In practice, it is not desirable to
Page 93 and 94: and decrease in amplitude mismatch
Page 95 and 96: Current interactionThe two oscillat
Page 97 and 98: equirements. Fortunately, by connec
Page 99 and 100: LC oscillators are put apart to red
Page 101 and 102: Gain mismatch (in %)Two oscillators
Page 103 and 104: equals to1 . By doubling the height
Page 105 and 106: 30 is obtained. It is because the s
Page 107 and 108: The spiral inductor is designed and
Page 109 and 110: oscillators (shown in the upper and
Page 111 and 112: Synthesizer LayoutThe layout and th
Page 113 and 114: Die LayoutFig. 98 shows the die pho
Page 115 and 116: Testing setupThe testing setup show
Page 117 and 118: Resistance (ohms)Freq (Hz)Fig. 101
Page 119 and 120: Resistance (ohms)Freq (Hz)Fig. 105
Page 121 and 122: VaractorFig. 109 shows the testing
Page 123 and 124: Table 5 Summary of parameters of va
Page 125 and 126: Table 6 Summary of N-well substrate
Page 127 and 128: Fig. 120 Quality factor of the swit
Page 129 and 130: The decrease in quality factor is d
Page 131 and 132: Fig. 126 Schematic diagram of the p
Page 133 and 134: Output frequency(MHz)Number of swit
Page 135 and 136: Gain (MHz/V)Tuning voltage (v)Fig.
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on the process variation. Therefore
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voltage (Vos = Rp x Ios) appeared.
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Although the spurs are quite large,
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GMSK signals with 0.3 BT and a bit
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Power spectral density (dB)(b)(a)(c
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Summary of performanceA summary of
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Table 10 Comparison of performances
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As the voltage-controlled oscillato
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Bibliography1 Thomas H. Lee, The De
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MPhil thesis of Lo Chi Wa - Department of Electronic & Computer ...

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