MPhil thesis of Lo Chi Wa - Department of Electronic & Computer ...

atio 5 in the other 50% of time. The average division ratio will be 4.5. This is referredto a fractional-N frequency synthesizer.The fractional-N frequency synthesizer is actually an integer-N frequency synthesizerwith a changing division ratio in the frequency divider. Only some additional digitalcircuits are needed to generate a continuously changing division ratio. This makes thedesign to be more simple and robust than the multi-loop frequency synthesizer asmultiple hardware of the multi-loops, filters and mixers are needed in multi-loopfrequency synthesizer. Therefore, this design is based on fractional-N PLL architecture.Design criteriaOne drawback of the fractional-N synthesizer is that quantization noise is added to theloop because there are only a few division ratios (quantization level) in the frequencydivider but they will represent the division ratios in between. In the case of a constantfractional division ratio required, the quantization noise generated is a single frequencytone, as shown in Fig. 17a, in which the frequency depends on the fractional divisionratio. In case of a random changing division ratio required, the quantization noisegenerated has a white noise spectrum as shown in Fig. 17b. To solve the problem, asigma-delta modulator can be used before the divider 10 . For a fractional number input(Fig. 18a), the sigma-delta modulator can redistribute the quantization noise such thatthe most of the noise is located at higher frequencies (Fig. 18b). The resultant highfrequency noise can be filtered out by the low-pass response of the loop (Fig. 18c), andvery little noise is left.26