MPhil thesis of Lo Chi Wa - Department of Electronic & Computer ...

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ImplementationIn this design, all capacitors are implemented by linear capacitors. Silicide-blocked polyis used to implement most of the resistors while NMOS transistors are used toimplement the largest resistor, as shown in Fig. 37. This non-linear resistor by NMOStransistors can be used because of the small variation of the tuning voltage. This resistoris designed to be the largest and the loop gain is the largest in the normal operationregion, 0.55V, as shown in Fig. 38. The 1/gm of the upper transistor will becomesmaller if input is smaller than 0.55V while the 1/gm of the lower diode-connectedtransistor will become smaller if input is larger than 0.55V. This can guarantee thestability of the loop even out of the normal operation region.Vtune_refVbiasRVinFig. 37 Schematic of the largest resistor implemented by NMOS transistors52
RVinFig. 38 Resistance of NMOS resistor vs. input voltageCharge pumpIn order to provide the two paths with different gains, two charge-pumps of differentsizes used. The charge-pumps are simple current steering charge-pumps with transistorswitches in saturation region for large output impedance. The output voltage range ofthe charge-pumps can be very small because of the nearly constant tuning voltage of theVCO, around 0.55V. In order to maintain the switches in the charge-pumps insaturation region, around 1V is needed to turn on the NMOS switches. Usually aresistive potential divider can generate the required 1V for the switches. However, sincea resistive potential divider requires small impedance for fast switching, it consumes alot of DC power. A simple switch capacitor driving stage, as shown in Fig. 40, isdesigned to drive the saturated transistor switches. When the input is high, all theNMOS switches are turned on and discharge all the capacitors to zero. When the inputis low, the PMOS switch is turned on and charge up the two capacitors in serial. Due tothe ratio between the two capacitors, when the upper electrode of the upper capacitor ischarged to 1.5V, the middle point between the two capacitors will become 1V. This53
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A 1.5-V 900-Mhz Monolithic CMOSFast
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A 1.5-V 900-Mhz Monolithic CMOS Fas
Page 5 and 6:
Table of ContentsPageAcknowledgment
Page 7 and 8:
Testing setup......................
Page 9 and 10:
List of FiguresPageFig. 1 Block dia
Page 11 and 12:
Fig. 76 Amplitudes and currents of
Page 13 and 14: Chapter 1 IntroductionBackgroundWir
Page 15 and 16: applications because it can provide
Page 17 and 18: existing monolithic frequency synth
Page 19 and 20: the receiver frequency band is from
Page 21 and 22: out-of-bandin-bandout-of-band0dBmin
Page 23 and 24: Based on the maximum interference,
Page 25 and 26: carrierdBcspur∆fFig. 8 Frequency
Page 27 and 28: Spurs requirement (dBc)Frequency of
Page 29 and 30: The frequency diversity can be perf
Page 31 and 32: Chapter 3 System DesignPhase-locked
Page 33 and 34: coarse tuning can be provided by th
Page 35 and 36: array is now possible. Moreover, th
Page 37 and 38: performance of the synthesizer 9 .
Page 39 and 40: signalquantizationnoisea) f b)signa
Page 41 and 42: esolution. The loop bandwidth is 80
Page 43 and 44: the output value between 0 and 0.5,
Page 45 and 46: The coupled-LC oscillators can be v
Page 47 and 48: 890MHzf25MHz243KHz865MHzFig. 23 Tun
Page 49 and 50: onoffCwellClinearCwellClinearCwellC
Page 51 and 52: spirals of similar sizes is around
Page 53 and 54: in Fig. 27a and Fig. 27b, the same
Page 55 and 56: conductance (Gm) and the reciprocal
Page 57 and 58: −19⎛ 900M⎞0.0259×1.6×10 ×
Page 59 and 60: GdoVinFig. 32 Gdo of the proposed L
Page 61 and 62: RzCzIcpCpR4C4a)IcpCzR4B.IcpCpRpC4b)
Page 63: Usually, capacitors in the filter o
Page 67 and 68: feedback path to prevent the proble
Page 69 and 70: 890MHz25MHz865MHzfA+∆A
Page 71 and 72: High-speed multi-modulus dividerThe
Page 73 and 74: CLKQBQDDBFig. 50 Schematic diagram
Page 75 and 76: ANDgateABclkclkclkclkQBFig. 54 Sche
Page 77 and 78: f o/2 /2,3 /2,3 /2 /2f div/4Combina
Page 79 and 80: next stage, as shown in the Fig. 59
Page 81 and 82: co10bDclkclkFig. 60 Schematic of th
Page 83 and 84: (1-Z -1 ) 23bDQBclkZ -1 (1-Z -1 )2b
Page 85 and 86: X 16clkDclkQBDclkQBFig. 66 Schemati
Page 87 and 88: ~90 oa) b) c)Fig. 68 Different meth
Page 89 and 90: (dotted line). As the oscillation c
Page 91 and 92: In practice, it is not desirable to
Page 93 and 94: and decrease in amplitude mismatch
Page 95 and 96: Current interactionThe two oscillat
Page 97 and 98: equirements. Fortunately, by connec
Page 99 and 100: LC oscillators are put apart to red
Page 101 and 102: Gain mismatch (in %)Two oscillators
Page 103 and 104: equals to1 . By doubling the height
Page 105 and 106: 30 is obtained. It is because the s
Page 107 and 108: The spiral inductor is designed and
Page 109 and 110: oscillators (shown in the upper and
Page 111 and 112: Synthesizer LayoutThe layout and th
Page 113 and 114: Die LayoutFig. 98 shows the die pho
Page 115 and 116:
Testing setupThe testing setup show
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Resistance (ohms)Freq (Hz)Fig. 101
Page 119 and 120:
Resistance (ohms)Freq (Hz)Fig. 105
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VaractorFig. 109 shows the testing
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Table 5 Summary of parameters of va
Page 125 and 126:
Table 6 Summary of N-well substrate
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Fig. 120 Quality factor of the swit
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The decrease in quality factor is d
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Fig. 126 Schematic diagram of the p
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Output frequency(MHz)Number of swit
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Gain (MHz/V)Tuning voltage (v)Fig.
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on the process variation. Therefore
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voltage (Vos = Rp x Ios) appeared.
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Although the spurs are quite large,
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GMSK signals with 0.3 BT and a bit
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Power spectral density (dB)(b)(a)(c
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Summary of performanceA summary of
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Table 10 Comparison of performances
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As the voltage-controlled oscillato
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Bibliography1 Thomas H. Lee, The De
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MPhil thesis of Lo Chi Wa - Department of Electronic & Computer ...

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