MPhil thesis of Lo Chi Wa - Department of Electronic & Computer ...

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Inductor layoutThe inductors used are double-layer (Metal 3 and Metal 2) circular spiral inductors. Forthe same inductance, circular spiral inductor has approximately pi/4 serial resistanceand parasitic capacitance of a square spiral inductor. The smaller serial resistance (orlarger quality factor) and parasitic capacitance can provide better phase noiseperformance and larger available tuning range of the voltage-controlled oscillator. Ourprevious trials show that single-layer and double-layer spiral inductors have a similarquality factor and parasitic capacitance. However, double-layer spiral inductor occupiesabout 1/4 area.The diameter of the spiral inductor is 280um with a hollow hole of 75um diameter. Thespacing between spirals is minimal, 1.8um. Since the sheet resistances of the two metallayers are different (0.05ohm for Metal 3 and 0.07ohm for Metal 2), the widths andnumbers of turns of the spirals of two layers are designed to be different to maintain thesame resistance per unit length, as shown in Fig. 90 and Fig. 91. In this case, the wholeresistance will not dominate by the spiral on the layer of higher resistance. The width ofthe spirals in Metal 2 and Metal 3 layers are 36um and 26um while the number of turnsare 2.5 and 3.5. These can keep the two spirals with the same resistance per length, thesame diameter and the same hollow hole size, as shown in Fig. 92. As the two spiralsoverlap and connect at the most inner turn, the two spirals share the resistance there.The same resistance per unit length can be still maintained even if the width of the innerturn of two spirals reduces. This special connection, as shown in Fig. 93, can maximizethe size of the hollow hole to improve the quality factor and reduce the parasiticcapacitance.94
The spiral inductor is designed and simulated by the ASITIC program. The inductanceis 6.6nH and the parallel parasitic capacitance is 0.6pF. However, since the programignores loss due to the substrate eddy current, the quality factor of the inductorcalculated by the program is totally incorrect. From previous trials, the quality factor ofspirals of similar sizes is around 2-2.5 which will dominate the overall quality factor ofthe whole LC tanks and limit the phase noise performance of the oscillator.Fig. 90 Layout of metal-2 layer of the inductorFig. 91 Layout of metal-3 layer of the inductor95
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A 1.5-V 900-Mhz Monolithic CMOSFast
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A 1.5-V 900-Mhz Monolithic CMOS Fas
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Table of ContentsPageAcknowledgment
Page 7 and 8:
Testing setup......................
Page 9 and 10:
List of FiguresPageFig. 1 Block dia
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Fig. 76 Amplitudes and currents of
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Chapter 1 IntroductionBackgroundWir
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applications because it can provide
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existing monolithic frequency synth
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the receiver frequency band is from
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out-of-bandin-bandout-of-band0dBmin
Page 23 and 24:
Based on the maximum interference,
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carrierdBcspur∆fFig. 8 Frequency
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Spurs requirement (dBc)Frequency of
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The frequency diversity can be perf
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Chapter 3 System DesignPhase-locked
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coarse tuning can be provided by th
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array is now possible. Moreover, th
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performance of the synthesizer 9 .
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signalquantizationnoisea) f b)signa
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esolution. The loop bandwidth is 80
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the output value between 0 and 0.5,
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The coupled-LC oscillators can be v
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890MHzf25MHz243KHz865MHzFig. 23 Tun
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onoffCwellClinearCwellClinearCwellC
Page 51 and 52:
spirals of similar sizes is around
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in Fig. 27a and Fig. 27b, the same
Page 55 and 56: conductance (Gm) and the reciprocal
Page 57 and 58: −19⎛ 900M⎞0.0259×1.6×10 ×
Page 59 and 60: GdoVinFig. 32 Gdo of the proposed L
Page 61 and 62: RzCzIcpCpR4C4a)IcpCzR4B.IcpCpRpC4b)
Page 63 and 64: Usually, capacitors in the filter o
Page 65 and 66: RVinFig. 38 Resistance of NMOS resi
Page 67 and 68: feedback path to prevent the proble
Page 69 and 70: 890MHz25MHz865MHzfA+∆A
Page 71 and 72: High-speed multi-modulus dividerThe
Page 73 and 74: CLKQBQDDBFig. 50 Schematic diagram
Page 75 and 76: ANDgateABclkclkclkclkQBFig. 54 Sche
Page 77 and 78: f o/2 /2,3 /2,3 /2 /2f div/4Combina
Page 79 and 80: next stage, as shown in the Fig. 59
Page 81 and 82: co10bDclkclkFig. 60 Schematic of th
Page 83 and 84: (1-Z -1 ) 23bDQBclkZ -1 (1-Z -1 )2b
Page 85 and 86: X 16clkDclkQBDclkQBFig. 66 Schemati
Page 87 and 88: ~90 oa) b) c)Fig. 68 Different meth
Page 89 and 90: (dotted line). As the oscillation c
Page 91 and 92: In practice, it is not desirable to
Page 93 and 94: and decrease in amplitude mismatch
Page 95 and 96: Current interactionThe two oscillat
Page 97 and 98: equirements. Fortunately, by connec
Page 99 and 100: LC oscillators are put apart to red
Page 101 and 102: Gain mismatch (in %)Two oscillators
Page 103 and 104: equals to1 . By doubling the height
Page 105: 30 is obtained. It is because the s
Page 109 and 110: oscillators (shown in the upper and
Page 111 and 112: Synthesizer LayoutThe layout and th
Page 113 and 114: Die LayoutFig. 98 shows the die pho
Page 115 and 116: Testing setupThe testing setup show
Page 117 and 118: Resistance (ohms)Freq (Hz)Fig. 101
Page 119 and 120: Resistance (ohms)Freq (Hz)Fig. 105
Page 121 and 122: VaractorFig. 109 shows the testing
Page 123 and 124: Table 5 Summary of parameters of va
Page 125 and 126: Table 6 Summary of N-well substrate
Page 127 and 128: Fig. 120 Quality factor of the swit
Page 129 and 130: The decrease in quality factor is d
Page 131 and 132: Fig. 126 Schematic diagram of the p
Page 133 and 134: Output frequency(MHz)Number of swit
Page 135 and 136: Gain (MHz/V)Tuning voltage (v)Fig.
Page 137 and 138: on the process variation. Therefore
Page 139 and 140: voltage (Vos = Rp x Ios) appeared.
Page 141 and 142: Although the spurs are quite large,
Page 143 and 144: GMSK signals with 0.3 BT and a bit
Page 145 and 146: Power spectral density (dB)(b)(a)(c
Page 147 and 148: Summary of performanceA summary of
Page 149 and 150: Table 10 Comparison of performances
Page 151 and 152: As the voltage-controlled oscillato
Page 153 and 154: Bibliography1 Thomas H. Lee, The De
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