Voltage References

Reading Flags
A read cycle need not be restricted to the vertical interval,
but may be done anytime. A flag read cycle consists of three
bytes (with three acknowledge bits):
• The first byte is always the Read address for the
MC44011 ($88).
• The second and third bytes are the flag data.
Communication begins when a start bit (data taken low
while clock is high), initiated by the master (nolthe MC44011),
is detected, generating an internal reset. The first byte
(address) is then entered, and if correct, an acknowledge is
Clock No.
10
1t
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
MC44011
generated by the MC44011. The flag bits will then exit the
MC44011 as two 8 bit bytes at clock cycles 10-17 and 19-26.
The master (receiving the data) is expected to generate the
acknowledge bits at clocks 18 and 27. The master must then
generate the stop bit.
The MC44011 flags must be read on a regular basis to
determine the status of the various circuit blocks. The
MC44011 does not generate interrupts. It is recommended
the flags be read once per field or frame. See Table 16 for a
description of the flags.
Table 16. Flag Description
Description (When Flag = 1)
Internally set to a Logic 1.
Horizontal Loop (PLL 1) enabled, indicating the loop can be driven by the incoming sync. This bit will be low upon power
up, and will change to a 1 after initialization of control Bit $86·6 and register $00.
Horizontal Loop (PLL 1) not locked. Lack of incoming sync, or wrong sync source selection, or the wrong horizontal
frequency, will cause the Coincidence Detector to indicate a "not locked" condition.
Internally set to Logic O.
Less than 576 horizontal lines counted per frame. This flag helps determine the applied video system. When high, a
525 line system (NTSC) is indicated. When low, a 625 line system (PAL) is indicated.
Vertical Countdown engaged. When high, this flag indicates the Vertical Countdown section has successfully
maintained lock for 8 consecutive fields, indicating therefor a successful vertical lock-up. This flag is low in the
Injection Lock mode.
Internally set to a Logic 1.
Internally set to a Logic 1.
(Acknowledge pulse).
Pixel clock VCO control voltage too low « 1.7 V at Pin 16). This indicates the VCO may not function correctly as the
control voltage is near one end of its range. The DAC setting at register $7F-5/0 must be increased, and/or the + 2
block must be selected (set $85-7 = 1), to clear this flag.
Pixel clock VCO control voltage too high (> 3.3 V at Pin 16). This indicates the VCO may not function correctly as the
control voltage is near one end of its range. The DAC setting at register $7F-5/0 must be reduced, and/or the + 2 block
must be deselected (set $85-7 = 0) to clear this flag. This flag will be high if the VCO is off (DAC $7F = 63).
Internally set to a Logic 1.
Internally set to a Logic O.
ACC Loop is active, indicating it is locked up to the color burst signal. The Color Burst amplitude must exceed
30 mVp_p, and the correct crystal selected, for lock-up to occur.
PAL system identified by the decoder, indicating the decoder recognizes the line-by-line change in the burst phase.
When NTSC is applied, this flag is O.
Not used.
Internally set to a Logic O.
(Acknowledge pulse).
MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-216