Voltage References

J
I Buffers
MC44807/17
BUS TIMING DIAGRAM
Standard Bus Protocol 18 or 19-Blt
4 5 t8 t9
Frequency
Bus Protocol for Test and Features
Data
Clock
Enable
L--'--__ _
t 4 5 t9 20 26 27 34
B3 B2 Bt BO Nt4 Nt3 Nt2 Ntt NtO N9 N8 N7 N6 N5 N4 N3 N2 Nt NO T6 T5 T4 T3 T2 Tt TO X7 X6 X5 X4 X3 X2 Xt xo
I Buffers Frequency Test and Features Random
J
Bus Protocol for 18-Blt
DEFINITION OF BUS PROTOCOLS
1 83 B2 Bt BO Nt3 Nt2 Ntt NtO N9 N8 N7 NS N5 N4 N3 N2 Nt
Max counting ratio 16363
N14 is reset internally
Bus Protocol for 19-Blt
I B3 B2 Bt BO Nt4 Nt3 Nt2 Ntt NtO N9 N8 N7 NS N5 N4 N3 N2 Nt
Max counting ratio 32767:
BO, Bl ... B3 = Control of band buffers N14 = MSB; NO = LSB
NO, Nl ... NI4 = Control of programmable divider Min, counting ratio always 17.
B3 = First shifted bit
NO = Last shifted bit
Bus Protocol for Test and Further Features (34-Blt)
I B3 B2 Bt BO Nt4 ... NO TS T5 T4 T3 T2 Tt TO X7
TO, Tl ... T3 = Control the phase comparator
T 4 = Switches test signals to the buffer outputs
T5 = Division ratio of the reference divider
T6 = Bypasses the prescaler (see note Bit T6 table)
XO, Xl ... X7 = Are random
B3 = First shifted bit
XO = Last shifted bit
MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
9-286
XS ... Xt
NO
NO
XO
L