Voltage References

MC33298
DYNAMIC ELECTRICAL CHARACTERISTICS (Characteristics noted under conditions of 4.75 V S VDD S 5.25 V, 9.0 V S VpWR
S 16 V, -40°C STC S 125°C, unless otherwise noted.)
POWER OUTPUT TIMING
Characteristic I Symbol I Min I Typ Max Unit
Output Rise Time (VPWR = 13 V, RL = 26 0) (Note 1) tr 1.0 1.5
Output Fall Time (VpWR = 13 V, RL = 26 0) (Note 1) tf 1.0 2.5
Output Turn ON Delay Time (VpWR = 13 V, RL = 26 0) (Note 2) tDLY(ON) 1.0 5.0
Output Turn OFF Delay Time (VPWR = 13 V, RL = 26 0) (Note 3) tDLY(ofl) 1.0 5.0
Output Short Fault Disable Report Delay (Note 4) tDLY(sf)
SFPD = 0.2 x VDD 25 50
Output OFF Fault Report Delay (Note 5) tDLY(ofl)
SFPD = 0.2 x VDD 25 50
NOTES: 1. Output Rise and Fall time respectively measured across a 26 n resistive load at 10% to 90% and 90% to 10% voltage points.
2. Output Turn ON Delay time measured from riSing edge of CSB to 50% of output OFF Vout voltage with Rl = 26 n resistive load
(see Figure 7 and 8).
3. Output Turn OFF Delay time measured from riSing edge of CSB to 50% of output OFF Vout voltage with Rl = 26 n resistive load
(see Figure 7 and 8).
4. Output Short Fault Disable Report Delay measured from rising edge of CSB to lout = 2.0 A point with output ON, Vout = 5.0 V,
and SFPD = 0.2 x VDD (see Figure 9 and 10).
5. Output OFF Fault Report Delay measured from 50% points of rising edge of CSB to rising edge of output (see Figure 8).
20 liS
20 liS
15 liS
15 liS
DYNAMIC ELECTRICAL CHARACTERISTICS (Characteristics noted under conditions of 4.75 V S VDD S 5.25 V, 9.0 V S VPWR
S 16 V, -40°C STC S 125°C, unless otherwise noted.)
Characteristic I Symbol I Min I Typ Max Unit
DIGITAL INTERFACE TIMING
SCLK Clock Period tpSCLK 500 - -
SCLK Clock High Time twSCLKH 250 - -
SCLK Clock Low Time twSCLKL 250 - -
Required Low State Duration for Reset (VIL S 0.2 VDD) (Note 1) IwRSTB 250 50 -
Falling Edge of CSB to Rising Edge of SCLK (Required Setup Time) tlead 250 50 -
Falling Edge of SCLK to Rising Edge of CSB (Required Setup Time) tlag 250 50 -
SI to Falling Edge of SCLK (Required Setup Time) tSISU 125 25 -
Falling Edge of SCLK to SI (Required Hold Time) tSI(hold) 125 25 -
SO Rise Time (CL = 120 pF) trSO - 25 50
SO Fall Time (CL = 120 pF) tfSO - 25 50
SI, CSB, SCLK Incoming Signal Rise Time (Note 2) trSI - - 200
SI, CSB, SCLK Incoming Signal Fall Time (Note 2) tfSI - - 200
Time from Falling Edge of CSB to SO
Low Impedance (Note 3) 1s0(en) - - 200
High Impedance (Note 4) tSO(dis) - - 200
Time from Rising Edge of SCLK to SO Data Valid (Note 5) !valid
0.2 VDD S SO