Voltage References

MC10321
TIMING CHARACTERISTICS (TA = 25'C, VCC = + 5.0 V, VEE = - 5.2 V, VRT = + 1.0 V, VRB = -1.0 V,
See System Timing Diagram)
INPUTS
Min Clock Pulse Width - High
-Low
Max Clock Rise, Fall Time
Clock Frequency
OUTPUTS
Parameter
New Data Valid from Clock Low
Aperture Delay
Hold Time
Data High to 3-State from Enable Low"
Data Low to 3-State from Enable Low"
Data High to 3-State from ENABLE High"
Data Low to 3-State from ENABLE High"
Valid Data from Enable High (Pin 14 = 0 V)"
Valid Data from ENABLE Low (Pin 13 = 5.0 V)"
Output Transition Time (10%-90%)"
·See Figure 2 for output loading.
TEMPERATURE CHARACTERISTICS
Parameter
ICC (+5.0 V Supply Current)
lEE (-5.2 V Supply Current)
Ladder Resistance
VOL (Output Low Voltage @ 4.0 mAl
VOH (Output High Voltage @ -400,.A)
Differential Nonlinearity
Integral Nonlinearity
PIN DESCRIPTIONS
Symbol Pin Description
GND 11,17 Power supply ground. The two pins should
be connected directly together, and
through a low impedance path to the
power supply.
OR 12 Overrange output. Indicates Yin is more
positive than VRT-1/2 LSB. This output
does not have 3-state capability, and therefore
is always active.
D6-DO 1-4, Digital Outputs. 06 (Pin 4) is the MSB, DO
16-20 (Pin 18) is the LSB. LSTTL compatible with
3-state capability.
VCC(D) 10,16 Power supply for the digital section.
+5.0 V, ± 10% required.
VEE 8 Negative Power supply. Nominally - 5.2 V,
it can range from - 3.0 to - 6.0 V, and must
be more negative than VRB by >1.3 V.
Yin 6 Signal voltage input. This voltage is compared
to the reference to generate a digital
equivalent. Input impedance is nominally
16-33 kfl (See Figure 4) in parallel with 22
pF.
Symbol Min Typ Max Units
tCKH - 5.0 - ns
tcKL - 15 -
tR F - 100 - ns
fCLK 0 30 25 MHz
tCKDV - 22 - ns
tAD - 3.0 - ns
tH - 6.0 - ns
tEHZ - 22 - ns
tELZ - 17 - ns
tE'HZ - 27 - ns
tE'LZ - 19 - ns
tEDV - 13 - ns
tE'DV - 20 - ns
ttr - 6.0 - ns
Typical Value Typical Change
@25"C - 40 to + 85"C
73mA -100 !LAI"C
-13mA + 7.0 !LAI"C
1400 +0.29%1'C
0.3 V +8.0/LVrC
3.0 V 2.1 mVrC
- - 0.0008 LSBrC
0.25 LSB -0.001 LSBrC
PIN DESCRIPTIONS
Symbol Pin Description
MOTOROLA LINEAR/INTERFACE ICs DEVICE DATA
6-48
VCC(A) 9 Power supply for the analog section.
+ 5.0 V, ± 10% required.
CLK 15 Clock input, TTL compatible, and can
range from dc to 25 MHz. Conversion
occurs on the negative edge of the clock.
EN 13 Enable input. TTL compatible, a Logic "1"
(and Pin 14 a Logic "0") enables the data
outputs. A Logic "0" sets the outputs
(except Overrange) to a 3-state mode.
Eli! 14 EIiIAm input. TTL compatible, a Logic
"0" (and Pin 13 a Logic "1") enables the
data outputs. A Logic "1" sets the outputs
(except Overrange) to a 3-state mode.
VRB 5 The bottom (most negative point) of the
internal reference resistor ladder. The ladder
resistance is typically 140 0 to VRT.
VRT 7 The top (most positive point) of the internal
reference resistor ladder.
Pin assignments are the 88me for the standard DIP package and the
surface mount package.