Avalon Interface Specifications (PDF) - Altera

2.1. Clock Sink
2. Avalon Clock and Reset Interfaces
Avalon Clock interfaces define the clock or clocks used by a component. Components
can have clock inputs, clock outputs, or both. A phase locked loop (PLL) is an
example of a component that has both a clock input and clock outputs. Figure 2–1 is a
simplified illustration showing the most important inputs and outputs of a PLL
component.
A typical component includes a clock sink input to provide a timing reference for
other interfaces and internal logic.
2.1.1. Clock Sink Signal Roles
Table 2–1. Clock Input Signal Roles
2.1.2. Clock Sink Properties
Figure 2–1. PLL Core Clock Outputs and Inputs
reset
ref_clk
PLL Core
Table 2–1 lists the clock input signals.
altpll Megafunction
Reset
Sink
Clock
Sink
Table 2–2 lists the properties of clock inputs.
Clock Output
Interface1
Clock Output
Interface2
Clock Output
Interface_n
May 2013 Altera Corporation Avalon Interface Specifications
Clock
Source
Clock
Source
Clock
Source
Signal Role Width Direction Required Description
clk 1 Input Yes
Table 2–2. Clock Sink Properties
A clock signal. Provides synchronization for internal logic and for
other interfaces.
Name Default Value Legal Values Description
clockRate 0 0–2 32 –1
Indicates the frequency in Hz of the clock sink interface. If 0, the clock
rate is not significant.