Avalon Interface Specifications (PDF) - Altera

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4–2 Chapter 4: Avalon Interrupt Interfaces Interrupt Receiver 4.2. Interrupt Receiver An interrupt receiver interface receives interrupts from interrupt sender interfaces. Components with an Avalon-MM master interface can include an interrupt receiver to detect interrupts asserted by slave components with interrupt sender interfaces. The interrupt receiver accepts interrupt requests from each interrupt sender as a separate bit. 4.2.1. Interrupt Receiver Signal Roles Table 4–3. Interrupt Receiver Signal Roles Table 4–3 lists the interrupt receiver signal roles. Signal Role Width Direction Required Description irq 1–32 Input Yes 4.2.2. Interrupt Receiver Properties Table 4–4. Interrupt Receiver Properties Table 4–4 lists the properties associated with interrupt receivers. A irq is an -bit vector, where each bit corresponds directly to one IRQ sender, with no inherent assumption of priority. Property Name Default Value Legal Values Description associatedAddressable Point — associatedClock — associatedReset — Name of Avalon-MM master interface Name of an Avalon Clock interface Name of an Avalon Reset interface irqScheme individualRequests individualRequests The name of the Avalon-MM master interface used to service interrupts received on this interface. The name of the Avalon Clock interface to which this interrupt receiver is synchronous. The sender and receiver may have different values for this property. The name of the reset interface to which this interrupt receiver is synchronous. Each interrupt sender interface asserts its irq signal to request service. Avalon Interface Specifications May 2013 Altera Corporation
Chapter 4: Avalon Interrupt Interfaces 4–3 Interrupt Receiver 4.2.3. Interrupt Timing Figure 4–1 illustrates interrupt timing. The Avalon-MM master services the priority 0 interrupt before the priority 1 interrupt. Figure 4–1. Interrupt Timing for Individual Request and Priority Encoded Interrupts Notes to Figure 4–1: (1) Interrupt 0 serviced. (2) Interrupt 1 serviced. Individual Requests clk int0 int1 1 2 May 2013 Altera Corporation Avalon Interface Specifications
Page 1 and 2: Avalon Interface Specifications 101
Page 3 and 4: Contents Chapter 1. Introduction 1.
Page 5 and 6: 1. Introduction Avalon ® interface
Page 7 and 8: Chapter 1: Introduction 1-3 In Figu
Page 9 and 10: Chapter 1: Introduction 1-5 Related
Page 11 and 12: 2.1. Clock Sink 2. Avalon Clock and
Page 13 and 14: Chapter 2: Avalon Clock and Reset I
Page 15 and 16: 3.1. Introduction 3. Avalon Memory-
Page 17 and 18: Chapter 3: Avalon Memory-Mapped Int
Page 31: 4.1. Interrupt Sender 4. Avalon Int
Page 35 and 36: 5. Avalon Streaming Interfaces You
Page 37 and 38: Chapter 5: Avalon Streaming Interfa
Page 45 and 46: 6. Avalon Conduit Interfaces Avalon
Page 47 and 48: Figure 7-1. Shared Pin Types Bidire
Page 49 and 50: Chapter 7: Avalon Tristate Conduit
Page 51 and 52: Document Revision History How to Co

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