Avalon Interface Specifications (PDF) - Altera

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5–8 Chapter 5: Avalon Streaming Interfaces Data Transfer with Backpressure When readyLatency >= 1, the sink asserts ready before the ready cycle itself. The source can respond during the appropriate cycle by asserting valid. It may not assert valid during a cycle that is not a ready cycle. Figure 5–6 illustrates an Avalon-ST interface where readyLatency = 4. Figure 5–6. Avalon-ST Interface with readyLatency = 4 clock ready valid data[31:0] readyLatency = 4 readyLatency = 4 source may not assert valid source may assert valid 1 2 3 4 Figure 5–7 illustrates a transfer with backpressure and readyLatency=0. The source provides data and asserts valid on cycle 1, even though the sink is not ready. The source waits until cycle two, when the sink does assert ready, before moving onto the next data cycle. In cycle 3, the source drives data on the same cycle and the sink is ready to receive it; the transfer happens immediately. In cycle 4, the sink asserts ready, but the source does not drive valid data. Figure 5–7. Transfer with Backpressure, readyLatency=0 clk ready valid channel error data 0 1 2 3 4 5 6 7 8 D0 D1 D2 D3 Avalon Interface Specifications May 2013 Altera Corporation
Chapter 5: Avalon Streaming Interfaces 5–9 Packet Data Transfers Figure 5–8 and Figure 5–9 show data transfers with readyLatency=1 and readyLatency=2, respectively. In both these cases, ready is asserted before the ready cycle, and the source responds 1 or 2 cycles later by providing data and asserting valid. When readyLatency is not 0, the source must deassert valid on non-ready cycles. Figure 5–8. Transfer with Backpressure, readyLatency=1 Figure 5–9. Transfer with Backpressure, readyLatency=2 5.11. Packet Data Transfers clk ready valid channel error data D0 D1 D2 D3 D4 D5 valid channel error data D0 D1 D2 The packet transfer property adds support for transferring packets from a source interface to a sink interface. Three additional signals are defined to implement the packet transfer. Both the source and sink interfaces must include these additional signals to support packets. No automatic adaptation is provided to create connections between source and sink interfaces with and without packet support. Figure 5–10. Avalon-ST Packet Interface Signals Data Source Data Sink valid data error channel startofpacket endofpacket empty May 2013 Altera Corporation Avalon Interface Specifications ready
Page 1 and 2: Avalon Interface Specifications 101
Page 3 and 4: Contents Chapter 1. Introduction 1.
Page 5 and 6: 1. Introduction Avalon ® interface
Page 7 and 8: Chapter 1: Introduction 1-3 In Figu
Page 9 and 10: Chapter 1: Introduction 1-5 Related
Page 11 and 12: 2.1. Clock Sink 2. Avalon Clock and
Page 13 and 14: Chapter 2: Avalon Clock and Reset I
Page 15 and 16: 3.1. Introduction 3. Avalon Memory-
Page 17 and 18: Chapter 3: Avalon Memory-Mapped Int
Page 31 and 32: 4.1. Interrupt Sender 4. Avalon Int
Page 33 and 34: Chapter 4: Avalon Interrupt Interfa
Page 35 and 36: 5. Avalon Streaming Interfaces You
Page 37 and 38: Chapter 5: Avalon Streaming Interfa
Page 39 and 40: Chapter 5: Avalon Streaming Interfa
Page 41: Chapter 5: Avalon Streaming Interfa
Page 45 and 46: 6. Avalon Conduit Interfaces Avalon
Page 47 and 48: Figure 7-1. Shared Pin Types Bidire
Page 49 and 50: Chapter 7: Avalon Tristate Conduit
Page 51 and 52: Document Revision History How to Co

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