Avalon Interface Specifications (PDF) - Altera

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2–2 Chapter 2: Avalon Clock and Reset Interfaces Clock Source 2.1.3. Associated Clock Interfaces Figure 2–2. associatedClock Property rx_clk 2.2. Clock Source All synchronous interfaces have an associatedClock property that specifies which clock input on the component is used as a synchronization reference for the interface. This property is illustrated in Figure 2–2. Clock Sink ST Sink An Avalon Clock source interface is an interface that drives a clock signal out of a component. 2.2.1. Clock Source Signal Roles Table 2–3 lists the clock source signals. 2.2.2. Clock Source Properties Dual Clock FIFO Table 2–4 lists the properties of clock outputs. Avalon Interface Specifications May 2013 Altera Corporation ST Source tx_clk rx_data tx_data associatedClock = "rx_clk" associatedClock = "tx_clk" Table 2–3. Clock Source Signal Roles Signal Role Width Direction Required Description clk 1 Output Yes An output clock signal. Table 2–4. Clock Source Properties Name Default Value Legal Values Description associatedDirect Clock — a clock name clockRate 0 0–2 32 –1 clockRateKnown false true, false Clock Sink The name of the clock input that directly drive this clock output, if any. Indicates the frequency in Hz at which the clock output is driven. Indicates whether or not the clock frequency is known. If the clock frequency is known, this information can be used to customize other components in the system.
Chapter 2: Avalon Clock and Reset Interfaces 2–3 Reset Interfaces 2.3. Reset Interfaces 2.3.1. Reset Sink Table 2–5. Reset Input Signal Roles Avalon Reset interfaces provide both soft and hard reset functionality. Soft reset logic typically reinitializes registers and memories without powering down the device. Hard reset logic initializes the device after power-on. The following sections describe the properties and signal roles for reset interfaces. Table 2–5 lists the reset input signals. Signal Role Width Direction Required Description reset reset_n 2.3.2. Reset Sink Interface Properties Table 2–6 lists the properties of resets. 2.3.3. Associated Reset Interfaces 2.3.4. Reset Source 1 Input Yes Table 2–6. Reset Interface Properties All synchronous interfaces have an associatedReset property that specifies which reset signal resets the interface logic. Table 2–7 lists the reset input signals. Resets the internal logic of an interface or component to a user-defined state. Synchronous to the clock input in the associated clock interface. Name Default Value Legal Values Description associatedClock — a clock name synchronousEdges DEASSERT Table 2–7. Reset Output Signal Roles NONE DEASSERT BOTH The name of a clock to which this interface synchronized. Required if the value of synchronousEdges is DEASSERT or BOTH. Indicates the type of synchronization the reset input requires. The following values are defined: ■ NONE–no synchronization is required because the component includes logic for internal synchronization of the reset signal. ■ DEASSERT–the reset assertion is asynchronous and deassertion is synchronous. ■ BOTH–reset assertion and deassertion are synchronous. Signal Role Width Direction Required Description reset reset_n 1 Output Yes Resets the internal logic of an interface or component to a user-defined state. May 2013 Altera Corporation Avalon Interface Specifications
Page 1 and 2: Avalon Interface Specifications 101
Page 3 and 4: Contents Chapter 1. Introduction 1.
Page 5 and 6: 1. Introduction Avalon ® interface
Page 7 and 8: Chapter 1: Introduction 1-3 In Figu
Page 9 and 10: Chapter 1: Introduction 1-5 Related
Page 11: 2.1. Clock Sink 2. Avalon Clock and
Page 15 and 16: 3.1. Introduction 3. Avalon Memory-
Page 17 and 18: Chapter 3: Avalon Memory-Mapped Int
Page 31 and 32: 4.1. Interrupt Sender 4. Avalon Int
Page 33 and 34: Chapter 4: Avalon Interrupt Interfa
Page 35 and 36: 5. Avalon Streaming Interfaces You
Page 37 and 38: Chapter 5: Avalon Streaming Interfa
Page 45 and 46: 6. Avalon Conduit Interfaces Avalon
Page 47 and 48: Figure 7-1. Shared Pin Types Bidire
Page 49 and 50: Chapter 7: Avalon Tristate Conduit
Page 51 and 52: Document Revision History How to Co

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