Avalon Interface Specifications (PDF) - Altera

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7–2 Chapter 7: Avalon Tristate Conduit Interface Figure 7–2. Tristate Conduit Interfaces Altera FPGA TCM Tristate Conduit Master TCS Tristate Conduit Slave S Avalon-MM Master clock Avalon-MM Slave S S Figure 7–2 illustrates the typical use of Avalon-TC Master and Slave interfaces and signal naming. Controller for 2 MByte x32 SSRAM Controller for 8 MByte x16 Flash TCM CS IRQ A[20:0] D_EN D[31:0] DI[31:0] Rd Wr Request Grant TCM Grant Req A[22:0] D_EN D[15:0] DI[15:0] Rd Wr CS IRQ chipselect_out addr_out[20:0] data_outen data_out[31:0] data_in[31:0] read_out write_out request grant grant request addr_out[22:0] data_outen data_out[15:0] data_in[15:0] read_out write_out chipselect_out irq_in TCS Arb TCS Tristate Conduit Pin Sharer f For more information about the Generic Tristate Controller and Tristate Conduit Pin Sharer, refer to the Avalon Tristate Conduit Components User Guide and the Qsys Interconnect chapter in volume 1 of the Quartus II Handbook. Avalon Interface Specifications May 2013 Altera Corporation TCM request grant Tristate Conduit Bridge TCS chipselect_out addr_out data_outen data_out data_in read_out write_out chipselect_out irq_in
Chapter 7: Avalon Tristate Conduit Interface 7–3 Tristate Conduit Signals 7.1. Tristate Conduit Signals Table 7–1 lists the signal defined for the Avalon-TC interface. All Avalon-TC signals apply to both masters and slaves and have the same meaning for both Table 7–1. Tristate Conduit Interface Signal Roles Signal Role Width Direction Required Description request 1 grant 1 _in 1 – 1,024 _out 1 – 1,024 _outen 1 Master → Slave Slave → Master Slave → Master Master → Slave Master → Slave 7.2. Tristate Conduit Properties There are no special properties for the Avalon-TC Interface. 7.3. Tristate Conduit Timing Yes Yes The meaning of request depends on the state of the grant signal, as the following rules dictate. 1. When request is asserted and grant is deasserted, request is requesting access for the current cycle. 2. When request is asserted and grant is asserted, request is requesting access for the next cycle; consequently, request should be deasserted on the final cycle of an access. Because request is deasserted in the last cycle of a bus access, it can be reasserted immediately following the final cycle of a transfer, making both rearbitration and continuous bus access possible if no other masters are requesting access. Once asserted, request must remain asserted until granted; consequently, the shortest bus access is 2 cycles. Refer to Figure 7–3 on page 7–4 for an example of arbitration timing. When asserted, indicates that a tristate conduit master has been granted access to perform transactions. grant is asserted in response to the request signal and remains asserted until 1 cycle following the deassertion of request. The design of the Avalon-TC Interface does not allow a default Avalon-TC master to be granted when no masters are requesting. No The input signal of a logical tristate signal. No The output signal of a logical tristate signal. No The output enable for a logical tristate signal. Figure 7–3 illustrates arbitration timing for the Tristate Conduit Pin Sharer. As this figure illustrates, a device can drive or receive valid data in the granted cycle. Figure 7–3 shows the following sequence of events: 1. In cycle one, the tristate conduit master asserts grant. The granted slave drives valid data in cycles one and two. 2. In cycle 4, the tristate conduit master asserts grant. The granted slave drives valid data in cycles 4–7. May 2013 Altera Corporation Avalon Interface Specifications
Page 1 and 2: Avalon Interface Specifications 101
Page 3 and 4: Contents Chapter 1. Introduction 1.
Page 5 and 6: 1. Introduction Avalon ® interface
Page 7 and 8: Chapter 1: Introduction 1-3 In Figu
Page 9 and 10: Chapter 1: Introduction 1-5 Related
Page 11 and 12: 2.1. Clock Sink 2. Avalon Clock and
Page 13 and 14: Chapter 2: Avalon Clock and Reset I
Page 15 and 16: 3.1. Introduction 3. Avalon Memory-
Page 17 and 18: Chapter 3: Avalon Memory-Mapped Int
Page 31 and 32: 4.1. Interrupt Sender 4. Avalon Int
Page 33 and 34: Chapter 4: Avalon Interrupt Interfa
Page 35 and 36: 5. Avalon Streaming Interfaces You
Page 37 and 38: Chapter 5: Avalon Streaming Interfa
Page 45 and 46: 6. Avalon Conduit Interfaces Avalon
Page 47: Figure 7-1. Shared Pin Types Bidire
Page 51 and 52: Document Revision History How to Co

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