Avalon Interface Specifications (PDF) - Altera

2–2 Chapter 2: Avalon Clock and Reset Interfaces
Clock Source
2.1.3. Associated Clock Interfaces
Figure 2–2. associatedClock Property
rx_clk
2.2. Clock Source
All synchronous interfaces have an associatedClock property that specifies which
clock input on the component is used as a synchronization reference for the interface.
This property is illustrated in Figure 2–2.
Clock
Sink
ST
Sink
An Avalon Clock source interface is an interface that drives a clock signal out of a
component.
2.2.1. Clock Source Signal Roles
Table 2–3 lists the clock source signals.
2.2.2. Clock Source Properties
Dual Clock FIFO
Table 2–4 lists the properties of clock outputs.
Avalon Interface Specifications May 2013 Altera Corporation
ST
Source
tx_clk
rx_data tx_data
associatedClock = "rx_clk" associatedClock = "tx_clk"
Table 2–3. Clock Source Signal Roles
Signal Role Width Direction Required Description
clk 1 Output Yes An output clock signal.
Table 2–4. Clock Source Properties
Name Default Value Legal Values Description
associatedDirect
Clock
— a clock name
clockRate 0 0–2 32 –1
clockRateKnown false true, false
Clock
Sink
The name of the clock input that directly drive this clock output,
if any.
Indicates the frequency in Hz at which the clock output is
driven.
Indicates whether or not the clock frequency is known. If the
clock frequency is known, this information can be used to
customize other components in the system.