Avalon Interface Specifications (PDF) - Altera

3–8 Chapter 3: Avalon Memory-Mapped Interfaces
Transfers
3.5. Transfers
This section defines two basic concepts before introducing the transfer types:
■ Transfer—A transfer is a read or write operation of a word or symbol of data,
between an Avalon-MM port and the interconnect. Avalon-MM transfers words
ranging in size from 8–1024 bits. Transfers take one or more clock cycles to
complete.
Both masters and slaves are part of a transfer; the Avalon-MM master initiates the
transfer and the Avalon-MM slave responds to it.
■ Master-slave pair—This term refers to the master port and slave port involved in a
transfer. During a transfer, the master port's control and data signals pass through
the interconnect fabric and interact with the slave port.
3.5.1. Typical Read and Write Transfers
This section describes a typical Avalon-MM interface that supports read and write
transfers with slave-controlled waitrequest. The slave can stall the interconnect for as
many cycles as required by asserting the waitrequest signal. If a slave uses
waitrequest for either read or write transfers, it must use waitrequest for both.
If a slave receives address, byteenable, read or write, and writedata after the rising
edge of the clock, the slave port must assert waitrequest before the next rising clock
edge to hold off the transfers. When the slave asserts waitrequest, the transfer is
delayed and the address and control signals are held constant. Transfers complete on
the rising edge of the first clk after the slave port deasserts waitrequest.
There is no limit on how long a slave port can stall. Therefore, you must ensure that a
slave port does not assert waitrequest indefinitely. Figure 3–3 shows read and write
transfers using waitrequest for a system in which the master and slave both have a
readdatavalid signal.
Avalon Interface Specifications May 2013 Altera Corporation