Avalon Interface Specifications (PDF) - Altera

More documents

Recommendations

Info

2–4 Chapter 2: Avalon Clock and Reset Interfaces Reset Interfaces 2.3.5. Reset Source Interface Properties Table 2–8. Reset Interface Properties Table 2–6 lists the properties of resets. Name Default Value Legal Values Description associatedClock — a clock name associatedDirectReset — a reset name associatedResetSinks — a reset name synchronousEdges DEASSERT NONE DEASSERT BOTH The name of a clock to which this interface synchronized. Required if the value of synchronousEdges is DEASSERT or BOTH. The name of the reset input that directly drives this reset source through a one-to-one link. Specifies reset inputs which will eventually cause a reset source to assert reset; for example, a reset synchronizer ORs a number of reset inputs to generate a reset output. indicates the type of synchronization the reset input requires. The following values are defined: ■ NONE–no synchronization is required because the component includes logic for internal synchronization of the reset signal. ■ DEASSERT–the reset assertion is asynchronous and deassertion is synchronous. ■ BOTH–reset assertion and deassertion are synchronous. Avalon Interface Specifications May 2013 Altera Corporation
3.1. Introduction 3. Avalon Memory-Mapped Interfaces Avalon Memory-Mapped (Avalon-MM) interfaces are used for read and write interfaces on master and slave components in a memory-mapped system. These components include microprocessors, memories, UARTs, DMAs, and timers which have master and slave interfaces connected by an interconnect fabric. Avalon-MM interfaces can describe a wide variety of component interfaces, from SRAM interfaces which support simple, fixed-cycle read and write transfers to more complex, pipelined interfaces capable of burst transfers. Figure 3–1 shows a typical system, highlighting the Avalon-MM slave interface connection to the interconnect fabric. Figure 3–1. Focus on Avalon-MM Slave Transfers Avalon-MM System Avalon-MM Slave Flash Controller Tristate Conduit Slave Flash Memory Chip Processor Avalon-MM Master Avalon-MM Slave SRAM Controller Tristate Conduit Slave Tristate Conduit Pin Sharer & Tristate Conduit Bridge Tristate Conduit Master Tristate Conduit Slave SRAM Memory Chip Interconnect May 2013 Altera Corporation Avalon Interface Specifications Ethernet PHY Chip Ethernet MAC Custom Logic Avalon-MM Master Avalon-MM Slave RAM Controller RAM Memory Chip Avalon-MM Slave UART RS-232 Avalon-MM Master Avalon-MM Avalon Slave Port Custom Logic
Page 1 and 2: Avalon Interface Specifications 101
Page 3 and 4: Contents Chapter 1. Introduction 1.
Page 5 and 6: 1. Introduction Avalon ® interface
Page 7 and 8: Chapter 1: Introduction 1-3 In Figu
Page 9 and 10: Chapter 1: Introduction 1-5 Related
Page 11 and 12: 2.1. Clock Sink 2. Avalon Clock and
Page 13: Chapter 2: Avalon Clock and Reset I
Page 17 and 18: Chapter 3: Avalon Memory-Mapped Int
Page 31 and 32: 4.1. Interrupt Sender 4. Avalon Int
Page 33 and 34: Chapter 4: Avalon Interrupt Interfa
Page 35 and 36: 5. Avalon Streaming Interfaces You
Page 37 and 38: Chapter 5: Avalon Streaming Interfa
Page 45 and 46: 6. Avalon Conduit Interfaces Avalon
Page 47 and 48: Figure 7-1. Shared Pin Types Bidire
Page 49 and 50: Chapter 7: Avalon Tristate Conduit
Page 51 and 52: Document Revision History How to Co

Avalon Interface Specifications (PDF) - Altera

Create successful ePaper yourself

Delete template?

Save as template?