Avalon Interface Specifications (PDF) - Altera

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1–2 Chapter 1: Introduction Figure 1–1 and Figure 1–2 illustrate the use of the Avalon interfaces in system designs. Figure 1–1. Avalon Interfaces in a System Design with Scatter Gather DMA Controller and Nios II Processor Printed Circuit Board Altera FPGA IRQ4 IRQ3 C1 M S Src Snk Conduit Avalon-MM Master Avalon-MM Slave Avalon-ST Source Avalon-ST Sink Nios II C2 IRQ1 M C1 S CSrc CSnk PLL C1 Ref Clk CSrc C2 Cn TCM TCS CSrc CSnk UART Avalon Conduit Avalon-TC Master Avalon-TC Slave Avalon Clock Source Avalon Clock Sink IRQ2 C1 Avalon-MM Timer S C1 S FIFO Buffer SSRAM Flash DDR3 Tristate Cntrl SSRAM S C2 S S M S Scatter Gather DMA IRQ4 Cn Src Avalon-ST Avalon-ST Snk Ethernet Controller FIFO Buffer C2 S Snk Avalon-ST Avalon-ST Src Avalon Interface Specifications May 2013 Altera Corporation TCM Cn Cn Cn TCS Cn Tristate Conduit Bridge TCS TCM Tristate Conduit Pin Sharer C1 TCS TMS Tristate Cntrl Flash C2 M Scatter Gather DMA Cn DDR3 Controller IRQ3
Chapter 1: Introduction 1–3 In Figure 1–1, the Nios ® II processor accesses the control and status registers of on-chip components using an Avalon-MM interface. The scatter gather DMAs send and receive data using Avalon-ST interfaces. Four components include interrupt interfaces serviced by software running on the Nios II processor. A PLL accepts a clock via an Avalon Clock Sink interface and provides two clock sources. Two components include Avalon-TC interfaces to access off-chip memories. Finally, the DDR3 controller accesses external DDR3 memory using an Avalon Conduit interface. Figure 1–2. Avalon Interfaces in a System Design with PCI Express Endpoint and External Processor Printed Circuit Board Altera FPGA C1 Ethernet MAC IRQ1 IRQ2 IRQ3 Custom Logic M C1 M S S Tristate Cntrl SSRAM TCS TCS TCM TCM Tristate Conduit Pin Sharer SSRAM TCS TCM Tristate Conduit Bridge Cn Tristate Cntrl Flash Flash Avalon-MM C1 S SDRAM Controller Cn Cn Cn Cn SDRAM CSrc CSnk PLL C1 CSrc C2 May 2013 Altera Corporation Avalon Interface Specifications C1 C2 PCI Express Root Port PCI Express Endpoint M S UART IRQ4 Ref Clk IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 C1 C2 External CPU External Bus Protocol Bridge M S Custom Logic IRQ5
Page 1 and 2: Avalon Interface Specifications 101
Page 3 and 4: Contents Chapter 1. Introduction 1.
Page 5: 1. Introduction Avalon ® interface
Page 9 and 10: Chapter 1: Introduction 1-5 Related
Page 11 and 12: 2.1. Clock Sink 2. Avalon Clock and
Page 13 and 14: Chapter 2: Avalon Clock and Reset I
Page 15 and 16: 3.1. Introduction 3. Avalon Memory-
Page 17 and 18: Chapter 3: Avalon Memory-Mapped Int
Page 31 and 32: 4.1. Interrupt Sender 4. Avalon Int
Page 33 and 34: Chapter 4: Avalon Interrupt Interfa
Page 35 and 36: 5. Avalon Streaming Interfaces You
Page 37 and 38: Chapter 5: Avalon Streaming Interfa
Page 45 and 46: 6. Avalon Conduit Interfaces Avalon
Page 47 and 48: Figure 7-1. Shared Pin Types Bidire
Page 49 and 50: Chapter 7: Avalon Tristate Conduit
Page 51 and 52: Document Revision History How to Co

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