Avalon Interface Specifications (PDF) - Altera

5–8 Chapter 5: Avalon Streaming Interfaces
Data Transfer with Backpressure
When readyLatency >= 1, the sink asserts ready before the ready cycle itself. The
source can respond during the appropriate cycle by asserting valid. It may not assert
valid during a cycle that is not a ready cycle. Figure 5–6 illustrates an Avalon-ST
interface where readyLatency = 4.
Figure 5–6. Avalon-ST Interface with readyLatency = 4
clock
ready
valid
data[31:0]
readyLatency = 4 readyLatency = 4
source may not assert valid
source may assert valid
1 2 3 4
Figure 5–7 illustrates a transfer with backpressure and readyLatency=0. The source
provides data and asserts valid on cycle 1, even though the sink is not ready. The
source waits until cycle two, when the sink does assert ready, before moving onto the
next data cycle. In cycle 3, the source drives data on the same cycle and the sink is
ready to receive it; the transfer happens immediately. In cycle 4, the sink asserts ready,
but the source does not drive valid data.
Figure 5–7. Transfer with Backpressure, readyLatency=0
clk
ready
valid
channel
error
data
0 1 2 3 4 5 6 7 8
D0 D1 D2 D3
Avalon Interface Specifications May 2013 Altera Corporation