Avalon Interface Specifications (PDF) - Altera

4–2 Chapter 4: Avalon Interrupt Interfaces
Interrupt Receiver
4.2. Interrupt Receiver
An interrupt receiver interface receives interrupts from interrupt sender interfaces.
Components with an Avalon-MM master interface can include an interrupt receiver to
detect interrupts asserted by slave components with interrupt sender interfaces. The
interrupt receiver accepts interrupt requests from each interrupt sender as a separate
bit.
4.2.1. Interrupt Receiver Signal Roles
Table 4–3. Interrupt Receiver Signal Roles
Table 4–3 lists the interrupt receiver signal roles.
Signal Role Width Direction Required Description
irq 1–32 Input Yes
4.2.2. Interrupt Receiver Properties
Table 4–4. Interrupt Receiver Properties
Table 4–4 lists the properties associated with interrupt receivers.
A
irq is an -bit vector, where each bit corresponds directly to one
IRQ sender, with no inherent assumption of priority.
Property Name Default Value Legal Values Description
associatedAddressable
Point
—
associatedClock —
associatedReset —
Name of Avalon-MM
master interface
Name of an Avalon Clock
interface
Name of an Avalon Reset
interface
irqScheme individualRequests individualRequests
The name of the Avalon-MM
master interface used to
service interrupts received on
this interface.
The name of the Avalon Clock
interface to which this interrupt
receiver is synchronous. The
sender and receiver may have
different values for this
property.
The name of the reset interface
to which this interrupt receiver
is synchronous.
Each interrupt sender interface
asserts its irq signal to
request service.
Avalon Interface Specifications May 2013 Altera Corporation