Avalon Interface Specifications (PDF) - Altera

1–4 Chapter 1: Introduction
Avalon Properties and Parameters
In Figure 1–2, an external processor accesses the control and status registers of on-chip
components via an external bus bridge with an Avalon-MM interface. The PCI
Express root port controls devices on the printed circuit board and the other
components of the FPGA by driving an on-chip PCI Express endpoint with an
Avalon-MM master interface. An external processor handles interrupts from five
components. A PLL accepts a reference clock via a Avalon Clock sink interface and
provides two clock sources. The flash and SRAM memories use an Avalon-TC
interface to share FPGA pins. Finally, an SDRAM controller accesses an external
SDRAM memory using an Avalon Conduit interface.
1.1. Avalon Properties and Parameters
1.2. Signal Roles
1.3. Interface Timing
Avalon interfaces use properties to describe their behavior. For example, the
maxChannel property of Avalon-ST interfaces allows you to specify the number of
channels supported by the interface. The clockRate property of the Avalon Clock
interface provides the frequency of a clock signal. The specification for each interface
type defines all of its properties and specifies the default values.
Each of the Avalon interfaces defines a number of signal roles and their behavior.
Many signal roles are optional, allowing component designers the flexibility to select
only the signal roles necessary to implement the required functionality. For example,
the Avalon-MM interface includes optional beginbursttransfer and burstcount
signal roles for use in components that support bursting. The Avalon-ST interface
includes the optional startofpacket and endofpacket signal roles for interfaces that
support packets.
With the exception of Avalon Conduit interfaces, each interface may include only one
signal of each signal role. Active-low signals are permitted for many signal roles.
Active-high signals are generally used in this document.
Subsequent chapters of this document include timing information that describes
transfers for individual interface types. There is no guaranteed performance for any of
these interfaces; actual performance depends on many factors, including component
design and system implementation.
Most Avalon interfaces must not be edge sensitive to signals other than the clock and
reset because other signals may transition multiple times before they stabilize. The
exact timing of signals between clock edges varies depending upon the characteristics
of the selected Altera device. This specification does not specify electrical
characteristics. Refer to the appropriate device documentation for electrical
specifications.
Avalon Interface Specifications May 2013 Altera Corporation