Functional Description -- HPC II Controller, External Memory ... - Altera

emi_rm_004
2013.12.16
Note:
Partial Writes
When using ECC, you must initialize your entire memory content to zero before beginning to write
to the memory. If you do not initialize the content to zero, and if you read from uninitialized memory
locations without having first written to them, you will see junk data which will trigger an ECC
interrupt.
5-11
When a single-bit or double-bit error occurs, the ECC logic triggers the ecc_interrupt signal to inform
you that an ECC error has occurred. When a single-bit error occurs, the ECC logic reads the error address,
and writes back the corrected data. When a double-bit error occurs, the ECC logic does not do any error
correction but it asserts the avl_rdata_error signal to indicate that the data is incorrect. The
avl_rdata_error signal follows the same timing as the avl_rdata_valid signal.
Enabling autocorrection allows the ECC logic to delay all controller pending activities until the correction
completes. You can disable autocorrection and schedule the correction manually when the controller is idle
to ensure better system efficiency. To manually correct ECC errors, follow these steps:
1. When an interrupt occurs, read out the SBE_ERROR register. When a single-bit error occurs, the
SBE_ERROR register is equal to one.
2. Read out the ERR_ADDR register.
3. Correct the single-bit error by issuing a dummy write to the memory address stored in the ERR_ADDR
register. A dummy write is a write request with the local_be signal zero, that triggers a partial write
which is effectively a read-modify-write event. The partial write corrects the data at that address and
writes it back.
Partial Writes
The ECC logic supports partial writes.
Along with the address, data, and burst signals, the Avalon-MM interface also supports a signal vector,
local_be, that is responsible for byte-enable. Every bit of this signal vector represents a byte on the databus.
Thus, a logic low on any of these bits instructs the controller not to write to that particular byte, resulting
in a partial write. The ECC code is calculated on all bytes of the data-bus. If any bytes are changed, the IP
core must recalculate the ECC code and write the new code back to the memory.
For partial writes, the ECC logic performs the following steps:
1. The ECC logic sends a read command to the partial write address.
2. Upon receiving a return data from the memory for the particular address, the ECC logic decodes the
data, checks for errors, and then merges the corrected or correct dataword with the incoming information.
3. The ECC logic issues a write to write back the updated data and the new ECC code.
The following corner cases can occur:
• A single-bit error during the read phase of the read-modify-write process. In this case, the IP core corrects
the single-bit error first, increments the single-bit error counter and then performs a partial write to this
corrected decoded data word.
• A double-bit error during the read phase of the read-modify-write process. In this case, the IP core
increments the double-bit error counter and issues an interrupt. The IP core writes a new write word to
the location of the error. The ECC status register keeps track of the error information.
The following figures show partial write operations for the controller, for full and half rate configurations,
respectively.
Functional Description—HPC II Controller
Altera Corporation
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