Functional Description -- HPC II Controller, External Memory ... - Altera

emi_rm_004
2013.12.16
Command Generator
The command generator accepts commands from the front-end Avalon-ST interface and from local ECC
internal logic, and provides those commands to the timing bank pool.
Timing Bank Pool
The timing bank pool is a parallel queue that works with the arbiter to enable data reordering. The timing
bank pool tracks incoming requests, ensures that all timing requirements are met and, upon receiving
write-data-ready notification from the write data buffer, passes the requests to the arbiter in an ordered and
efficient manner.
Arbiter
The arbiter determines the order in which requests are passed to the memory device. When the arbiter
receives a single request, that request is passed immediately; however, when multiple requests are received,
the arbiter uses arbitration rules to determine the order in which to pass requests to the memory device.
Arbitration Rules
The arbiter uses the following arbitration rules:
• If only one master is issuing a request, grant that request immediately.
• If there are outstanding requests from two or more masters, the arbiter applies the following tests, in
order:
• Is there a read request? If so, the arbiter grants the read request ahead of any write requests.
• If neither of the above conditions apply, the arbiter grants the oldest request first.
Rank Timer
The rank timer maintains rank-specific timing information, and performs the following functions:
• Ensures that only four activates occur within a specified timing window.
• Manages the read-to-write and write-to-read bus turnaround time.
• Manages the time-to-activate delay between different banks.
Read Data Buffer and Write Data Buffer
The read data buffer receives data from the PHY and passes that data through the input interface to the
master. The write data buffer receives write data from the input interface and passes that data to the PHY,
upon approval of the write request.
ECC Block
The error-correcting code (ECC) block comprises an encoder and a decoder-corrector, which can detect
and correct single-bit errors, and detect double-bit errors. The ECC block can remedy errors resulting from
noise or other impairments during data transmission.
AFI and CSR Interfaces
The AFI interface provides communication between the controller and the physical layer logic (PHY). The
CSR interface provides communication with your system’s internal control status registers.
For more information about AFI signals, refer to AFI 3.0 Specification in the Functional Description - UniPHY
chapter.
Note:
Unaligned reads and writes on the AFI interface are not supported.
Command Generator
5-5
Functional Description—HPC II Controller
Altera Corporation
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