Functional Description -- HPC II Controller, External Memory ... - Altera

emi_rm_004
2013.12.16
Local Interface Signals
5-21
Signal Name
Direction
Description
column bits – 3
If the bank address is 2 bits wide, row is 13 bits wide and column is 10
bits wide, the local address is 22 bits wide.
(* chip bits is a derived value indicating the number of address bits
necessary to uniquely address every memory rank in the system; this
value is not user configurable.)
avl_be[]
(2)
Input
Byte enable signal, which you use to mask off individual bytes during
writes. avl_be is active high; mem_dm is active low.
To map avl_wdata and avl_be to mem_dq and mem_dm, consider
a full-rate design with 32-bit avl_wdata and 16-bit mem_dq.
avl_wdata = < 22334455 >< 667788AA ><
BBCCDDEE>
avl_be = < 1100 >< 0110 >< 1010 >
These values map to:
Mem_dq =
Mem_dm =
avl_
burstbegin (3)
avl_read_req
(4)
Input
Input
The Avalon burst begin strobe, which indicates the beginning of an
Avalon burst. Unlike all other Avalon-MM signals, the burst begin
signal does not stay asserted if avl_ready is deasserted.
For write transactions, assert this signal at the beginning of each burst
transfer and keep this signal high for one cycle per burst transfer, even
if the slave deasserts avl_ready. The IP core samples this signal at
the rising edge of phy_clk when avl_write_req is asserted.
After the slave deasserts the avl_ready signal, the master keeps all
the write request signals asserted until avl_ready signal becomes
high again.
For read transactions, assert this signal for one clock cycle when read
request is asserted and avl_addr from which the data should be
read is given to the memory. After the slave deasserts avl_ready
(waitrequest_n in Avalon interface), the master keeps all the read
request signals asserted until avl_ready becomes high again.
Read request signal. You cannot assert read request and write request
signals at the same time. The controller must deassert reset_phy_
clk_n before you can assert avl_read_req.
local_refresh_
req
Input
User-controlled refresh request. If Enable User Auto-Refresh Controls
option is turned on, local_refresh_req becomes available and
you are responsible for issuing sufficient refresh requests to meet the
memory requirements. This option allows complete control over when
refreshes are issued to the memory including grouping together
multiple refresh commands. Refresh requests take priority over read
and write requests, unless the IP core is already processing the requests.
Functional Description—HPC II Controller
Altera Corporation
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