Functional Description -- HPC II Controller, External Memory ... - Altera

emi_rm_004
2013.12.16
Table 5-12: Clock and Reset Signals
Clock and Reset Signals
5-17
Name
global_reset_n
pll_ref_clk
phy_clk
reset_phy_clk_n
aux_full_rate_clk
aux_half_rate_clk
dll_reference_clk
reset_request_n
Direction
Input
Input
Output
Output
Output
Output
Output
Output
Description
The asynchronous reset input to the
controller. The IP core derives all other reset
signals from resynchronized versions of this
signal. This signal holds the PHY, including
the PLL, in reset while low.
The reference clock input to PLL.
The system clock that the PHY provides to
the user. All user inputs to and outputs from
the controller must be synchronous to this
clock.
The reset signal that the PHY provides to the
user. The IP core asserts reset_phy_clk_
n asynchronously and deasserts
synchronously to phy_clk clock domain.
An alternative clock that the PHY provides
to the user. This clock always runs at the same
frequency as the external memory interface.
In half-rate designs, this clock is twice the
frequency of the phy_clk and you can use
it whenever you require a 2x clock. In fullrate
designs, the same PLL output as the
phy_clk signal drives this clock.
An alternative clock that the PHY provides
to the user. This clock always runs at half the
frequency as the external memory interface.
In full-rate designs, this clock is half the
frequency of the phy_clk and you can use
it, for example to clock the user side of a halfrate
bridge. In half-rate designs, or if the
Enable Half Rate Bridge option is turned on.
The same PLL output that drives the phy_
clk signal drives this clock.
Reference clock to feed to an externally
instantiated DLL.
Reset request output that indicates when the
PLL outputs are not locked. Use this signal
as a reset request input to any system-level
reset controller you may have. This signal is
always low when the PLL is trying to lock,
and so any reset logic using Altera advises
you detect a reset request on a falling edge
rather than by level detection.
Functional Description—HPC II Controller
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