Functional Description -- HPC II Controller, External Memory ... - Altera

emi_rm_004
2013.12.16
Figure 5-2: Memory Controller Architecture Block Diagram
HPC II Memory Controller Architecture
5-3
Memory Controller
Rank Timer
Avalon-ST Input Interface
Command
Generator
Write Data Buffer
Timing Bank
Pool
Arbiter
ECC
AFI Interface to PHY
Read Data Buffer
CSR Interface
Avalon-ST Input Interface
The Avalon-ST interface serves as the entry point to the memory controller, and provides communication
with the requesting data masters.
For information about the Avalon interface, refer to Avalon Interface Specifications.
AXI to Avalon-ST Converter
The HPC II memory controller includes an AXI to Avalon-ST converter for communication with the AXI
protocol. The AXI to Avalon-ST converter provides write address, write data, write response, read address,
and read data channels on the AXI interface side, and command, write data, and read data channels on the
Avalon-ST interface side.
Handshaking
The AXI protocol employs a handshaking process similar to the Avalon-ST protocol, based on ready and
valid signals.
Command Channel Implementation
Functional Description—HPC II Controller
Altera Corporation
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