Functional Description -- HPC II Controller, External Memory ... - Altera

5-26
Controller Interface Signals
Table 5-14: Interface Signals
emi_rm_004
2013.12.16
Signal Name
mem_dq[]
mem_dqs[]
mem_dqs_n[]
mem_ck
mem_ck_n
mem_addr[]
mem_ac_parity (1)
mem_ba[]
mem_cas_n
mem_cke[]
mem_cs_n[]
mem_dm[]
mem_odt
mem_ras_n
mem_we_n
parity_error_n (1)
mem_err_out_n (1)
Direction
Bidirectional
Bidirectional
Bidirectional
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
Description
Memory data bus. This bus is half the width of the local read
and write data busses.
Memory data strobe signal, which writes data into the memory
device and captures read data into the Altera device.
Inverted memory data strobe signal, which with the mem_dqs
signal improves signal integrity.
Clock for the memory device.
Inverted clock for the memory device.
Memory address bus.
Address or command parity signal generated by the PHY and
sent to the DIMM. DDR3 SDRAM only.
Memory bank address bus.
Memory column address strobe signal.
Memory clock enable signals.
Memory chip select signals.
Memory data mask signal, which masks individual bytes
during writes.
Memory on-die termination control signal.
Memory row address strobe signal.
Memory write enable signal.
Active-low signal that is asserted when a parity error occurs
and stays asserted until the PHY is reset. DDR3 SDRAM only
Signal sent from the DIMM to the PHY to indicate that a parity
error has occured for a particular cycle. DDR3 SDRAM only.
Altera Corporation
Functional Description—HPC II Controller
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