Functional Description -- HPC II Controller, External Memory ... - Altera

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5-4 Backpressure Support The AXI interface includes separate read and write channels, while the Avalon-ST interface has only one command channel. Arbitration of the read and write channels is based on these policies: • Round robin • Write priority—write channel has priority over read channel • Read priority—read channel has priority over write channel You can choose an arbitration policy by setting the COMMAND_ARB_TYPE parameter to one of ROUND_ROBIN, WRITE_PRIORITY, or READ_PRIORITY in the alt_mem_ddrx_axi_st_converter.v file. Data Ordering The AXI specification requires that write data IDs must arrive in the same order as write address IDs are received. Similarly, read data must be returned in the same order as its associated read address is received. Consequently, the AXI to Avalon-ST converter does not support interleaving of write data; all data must arrive in the same order as its associated write address IDs. On the read side, the controller returns read data based on the read addresses received. Burst Types The AXI to Avalon-ST converter supports the following burst types: emi_rm_004 2013.12.16 • Incrementing burst—the address for each transfer is an increment of the previous transfer address; the increment value depends on the size of the transfer. • Wrapping burst—similar to the incrementing burst, but wraps to the lower address when the burst boundary is reached. The starting address must be aligned to the size of the transfer. Burst length must be 2, 4, 8, or 16. The burst wrap boundary = burst size * burst length. Related Information Avalon Interface Specifications Backpressure Support The write response and read data channels do not support data transfer with backpressure; consequently, you must assert the ready signal for the write response and read data channels to 1 to ensure acceptance of data at any time. Figure 5-3: Data Transfer Without Backpressure clk rready rvalid rid rresp rdata D0 D1 D2 D3 For information about data transfer with and without backpressure, refer to the Avalon Interface Specifications. Related Information Avalon Interface Specifications Altera Corporation Functional Description—HPC II Controller Send Feedback
emi_rm_004 2013.12.16 Command Generator The command generator accepts commands from the front-end Avalon-ST interface and from local ECC internal logic, and provides those commands to the timing bank pool. Timing Bank Pool The timing bank pool is a parallel queue that works with the arbiter to enable data reordering. The timing bank pool tracks incoming requests, ensures that all timing requirements are met and, upon receiving write-data-ready notification from the write data buffer, passes the requests to the arbiter in an ordered and efficient manner. Arbiter The arbiter determines the order in which requests are passed to the memory device. When the arbiter receives a single request, that request is passed immediately; however, when multiple requests are received, the arbiter uses arbitration rules to determine the order in which to pass requests to the memory device. Arbitration Rules The arbiter uses the following arbitration rules: • If only one master is issuing a request, grant that request immediately. • If there are outstanding requests from two or more masters, the arbiter applies the following tests, in order: • Is there a read request? If so, the arbiter grants the read request ahead of any write requests. • If neither of the above conditions apply, the arbiter grants the oldest request first. Rank Timer The rank timer maintains rank-specific timing information, and performs the following functions: • Ensures that only four activates occur within a specified timing window. • Manages the read-to-write and write-to-read bus turnaround time. • Manages the time-to-activate delay between different banks. Read Data Buffer and Write Data Buffer The read data buffer receives data from the PHY and passes that data through the input interface to the master. The write data buffer receives write data from the input interface and passes that data to the PHY, upon approval of the write request. ECC Block The error-correcting code (ECC) block comprises an encoder and a decoder-corrector, which can detect and correct single-bit errors, and detect double-bit errors. The ECC block can remedy errors resulting from noise or other impairments during data transmission. AFI and CSR Interfaces The AFI interface provides communication between the controller and the physical layer logic (PHY). The CSR interface provides communication with your system’s internal control status registers. For more information about AFI signals, refer to AFI 3.0 Specification in the Functional Description - UniPHY chapter. Note: Unaligned reads and writes on the AFI interface are not supported. Command Generator 5-5 Functional Description—HPC II Controller Altera Corporation Send Feedback
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