Functional Description -- HPC II Controller, External Memory ... - Altera

5-22
Local Interface Signals
emi_rm_004
2013.12.16
Signal Name
local_refresh_
chip
avl_size[] (5)
avl_wdata[] (6)
avl_write_
req (7)
Direction
Input
Input
Input
Input
Description
Controls which chip to issue the user refresh to. The IP core uses this
active high signal with local_refresh_req. This signal is as wide
as the memory chip select. This signal asserts a high value to each bit
that represents the refresh for the corresponding memory chip.
For example: If local_refresh_chip signal is assigned with a
value of 4’b0101, the controller refreshes the memory chips 0 and
2, and memory chips 1 and 3 are not refreshed.
Controls the number of beats in the requested read or write access to
memory, encoded as a binary number. In UniPHY, the IP core supports
Avalon burst lengths from 1 to 1024. The IP core derives the width of
this signal based on the burst count that you specify in the Maximum
Avalon-MM burst length option. With the derived width, you specify
a value ranging from 1 to the local maximum burst count specified.
This signal must remain stable only during the first transaction of a
burst. The constantBurstBehavior property is always false for
UniPHY controllers.
Write data bus. The width of avl_wdata is twice that of the memory
data bus for a full-rate controller, four times the memory data bus for
a half-rate controller, and eight times the memory data bus for a
quarter-rate controller. If Generate power-of-2 data bus widths for
Qsys and SOPC Builder is enabled, the width is rounded down to the
nearest power of 2.
Write request signal. You cannot assert read request and write request
signal at the same time. The controller must deassert reset_phy_
clk_n before you can assert avl_write_req.
local_autopch_
req (8)
Input
Input
User control of autoprecharge. If you turn on Enable Auto- Precharge
Control, the local_autopch_req signal becomes available and
you can request the controller to issue an autoprecharge write or
autoprecharge read command.
These commands cause the memory to issue a precharge command
to the current bank at the appropriate time without an explicit
precharge command from the controller. This feature is particularly
useful if you know the current read or write is the last one you intend
to issue to the currently open row. The next time you need to use that
bank, the access could be quicker as the controller does not need to
precharge the bank before activating the row you wish to access.
Upon receipt of the local_autopch_req signal, the controller
evaluates the pending commands in the command buffer and
determines the most efficient autoprecharge operation to perform,
reordering commands if necessary.
The controller must deassert reset_phy_clk_n before you can
assert local_autopch_req.
Altera Corporation
Functional Description—HPC II Controller
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