Functional Description -- HPC II Controller, External Memory ... - Altera

5-20
Local Interface Signals
emi_rm_004
2013.12.16
Signal Name
Direction
Description
Memory address at which the burst should start. By default, the IP
core maps local address to the bank interleaving scheme. You can
change the ordering via the Local-to-Memory Address Mapping
option in the Controller Settings page.
This signal must remain stable only during the first transaction of a
burst. The constantBurstBehavior property is always false for
UniPHY controllers.
The IP core sizes the width of this bus according to the following
equations:
• Full rate controllers:
For one chip select: width = row bits + bank bits + column bits – 1
For multiple chip selects: width = chip bits* + row bits + bank bits +
column bits – 1
If the bank address is 2 bits wide, row is 13 bits wide and column is 10
bits wide, the local address is 24 bits wide. To map local_address
to bank, row and column address:
avl_addr is 24 bits wide
avl_addr[23:11]= row address[12:0]
avl_addr[10:9] = bank address [1:0]
avl_addr[8:0] = column address[9:1]
The IP core ignores the least significant bit (LSB) of the column address
(multiples of two) on the memory side, because the local data width
is twice that of the memory data bus width.
• Half rate controllers:
For one chip select: width = row bits + bank bits + column bits – 2
For multiple chip selects: width = chip bits* + row bits + bank bits +
column bits – 2
If the bank address is 2 bits wide, row is 13 bits wide and column is 10
bits wide, the local address is 23 bits wide. To map local_address
to bank, row and column address:
avl_addr is 23 bits wide
avl_addr[22:10] = row address[12:0]
avl_addr[9:8] = bank address [1:0]
avl_addr[7:0] = column address[9:2]
The IP core ignores two LSBs of the column address (multiples of four)
on the memory side, because the local data width is four times that of
the memory data bus width.
• Quarter rate controllers:
For one chip select: width = row bits + bank bits + column bits – 3
For multiple chip selects: width = chip bits* + row bits + bank bits +
Altera Corporation
Functional Description—HPC II Controller
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