Functional Description -- HPC II Controller, External Memory ... - Altera

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5-34 Sequence of Operations Write Command When a requesting master issues a write command together with write data, the following events occur: • The input interface accepts the write command and the write data. • The input interface passes the write command to the command generator and the write data to the write data buffer. • The command generator processes the command and sends it to the timing bank pool. • Once all timing requirements are met and a write-data-ready notification has been received from the write data buffer, the timing bank pool sends the command to the arbiter. • When rank timing requirements are met, the arbiter grants the command request from the timing bank pool and passes the write command to the AFI interface. • The AFI interface receives the write command from the arbiter and requests the corresponding write data from the write data buffer. • The PHY receives the write command and the write data, through the AFI interface. Read Command When a requesting master issues a read command, the following events occur: • The input interface accepts the read command. • The input interface passes the read command to the command generator. • The command generator processes the command and sends it to the timing bank pool. • Once all timing requirements are met, the timing bank pool sends the command to the arbiter. • When rank timing requirements are met, the arbiter grants the command request from the timing bank pool and passes the read command to the AFI interface. • The AFI interface receives the read command from the arbiter and passes the command to the PHY. • The PHY receives the read command through the AFI interface, and returns read data through the AFI interface. • The AFI interface passes the read data from the PHY to the read data buffer. • The read data buffer sends the read data to the master through the input interface. Read-Modify-Write Command A read-modify-write command can occur when enabling ECC for partial write, and for ECC correction commands. When a read-modify-write command is issued, the following events occur: emi_rm_004 2013.12.16 • The command generator issues a read command to the timing bank pool. • The timing bank pool and arbiter passes the read command to the PHY through the AFI interface. • The PHY receives the read command, reads data from the memory device, and returns the read data through the AFI interface. • The read data received from the PHY passes to the ECC block. • The read data is processed by the write data buffer. • When the write data buffer issues a read-modify-write data ready notification to the command generator, the command generator issues a write command to the timing bank pool. The arbiter can then issue the write request to the PHY through the AFI interface. • When the PHY receives the write request, it passes the data to the memory device. Altera Corporation Functional Description—HPC II Controller Send Feedback
emi_rm_004 2013.12.16 Document Revision History 5-35 Document Revision History Date December 2013 November 2012 June 2012 November 2011 Version 2013.12.16 2.1 2.0 1.1 Changes • Removed references to ALTMEMPHY. • Removed references to SOPC Builder. • Removed Half-Rate Bridge information. • Modified Burst Merging description. • Expanded description of avl_ready in Local Interface Signals table. • Added descriptions of local_cal_success and local_cal_fail to Local Interface Signals table. • Modified description of avl_size in Local Interface Signals table. • Added guidance to initialize memory before use. • Added Controller Register Map information. • Added Burst Merging information. • Updated User-Controlled Refresh Interface information. • Changed chapter number from 4 to 5. • Added LPDDR2 support. • Added Feedback icon. • Revised Figure 5–1. • Added AXI to Avalon-ST Converter information. • Added AXI Data Slave Interface information. • Added Half-Rate Bridge information. Functional Description—HPC II Controller Altera Corporation Send Feedback
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