Functional Description -- HPC II Controller, External Memory ... - Altera

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5-30 Controller Register Map emi_rm_004 2013.12.16 Address Bit Name Default Access Description 0x121 31:0 Data width representation (word) — Read only The number of DQS bits in the memory interface. This bit can be used to derive the width of the memory interface by multiplying this value by the number of DQ pins per DQS pin (typically 8). 0x122 7:0 Chip select representation — Read only The number of chip select in binary representation. For example, a design with 2 chip selects has the value of 00000011. 31:8 Reserved. 0 — Reserved for future use. 3:0 tRCD — Read write The activate to read or write a timing parameter. The range of legal values is 2-11 cycles. 7:4 tRRD — Read write The activate to activate a timing parameter. The range of legal values is 2-8 cycles. 11:8 tRP — Read write The precharge to activate a timing parameter. The range of legal values is 2-11 cycles. 0x123 15:12 tMRD — Read write The mode register load time parameter. This value is not used by the controller, as the controller derives the correct value from the memory type setting. 23:16 tRAS — Read write The activate to precharge a timing parameter. The range of legal values is 4-29 cycles. 31:24 tRC — Read write The activate to activate a timing parameter. The range of legal values is 8-40 cycles. 3:0 tWTR — Read write The write to read a timing parameter. The range of legal values is 1-10 cycles. 0x124 7:4 15:8 tRTP tFAW — — Read write Read write The read to precharge a timing parameter. The range of legal values is 2-8 cycles. The four-activate window timing parameter. The range of legal values is 6-32 cycles. 31:16 Reserved. 0 — Reserved for future use. Altera Corporation Functional Description—HPC II Controller Send Feedback
emi_rm_004 2013.12.16 Controller Register Map 5-31 Address Bit Name Default Access Description 15:0 tREFI — Read write The refresh interval timing parameter. The range of legal values is 780-6240 cycles. 0x125 23:16 tRFC — Read write The refresh cycle timing parameter. The range of legal values is 12-255 cycles. 31:24 Reserved. 0 — Reserved for future use. 3:0 Reserved. 0 — Reserved for future use. 7:4 Reserved. 0 — Reserved for future use. 0x126 11:8 15:12 Reserved. Reserved. 0 0 — — Reserved for future use. Reserved for future use. 23:16 Burst Length — Read write Value must match memory burst length. 31:24 Reserved. 0 — Reserved for future use. Functional Description—HPC II Controller Altera Corporation Send Feedback
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Functional Description -- HPC II Controller, External Memory ... - Altera

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