Functional Description -- HPC II Controller, External Memory ... - Altera

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5-14 Controller External Interfaces emi_rm_004 2013.12.16 signal; the controller then deasserts the acknowledge signal when the memory device is no longer in selfrefresh mode. Note: For multi-rank designs using the HPC II memory controller, a self-refresh and a user-refresh cannot be made to the same memory chip simultaneously. Also, the self-refresh ack signal indicates that at least one device has entered self-refresh, but does not necessarily mean that all devices have entered self-refresh. User-Controlled Refresh Interface The optional user-controlled refresh interface consists of a request signal, a chip select signal, and an acknowledgement signal. This interface provides increased control over worst-case read latency and enables you to issue refresh bursts during idle periods. This interface is clocked by afi_clk. When you assert a refresh request signal to instruct the controller to perform a refresh operation, that request takes priority over any outstanding read or write requests that might be in the command queue. In addition to the request signal, you must also choose the chip to be refreshed by asserting the refresh chip select signal along with the request signal. If you do not assert the chip select signal with the request signal, unexpected behavior may result. The controller attempts to perform a refresh as long as the refresh request signal is asserted; if you require only one refresh, you should deassert the refresh request signal after the acknowledgement signal is received. If you maintain the request signal high after the acknowledgement is sent, it would indicate that further refresh is required. You should deassert the request signal after the required number of acknowledgement/refresh is received from the controller. You can issue up to a maximum of nine consecutive refresh commands. Note: For multi-rank designs using the HPC II memory controller, a self-refresh and a user-refresh cannot be made to the same memory chip simultaneously. Configuration and Status Register (CSR) Interface The controller has a configuration and status register (CSR) interface that allows you to configure timing parameters, address widths, and the behavior of the controller. The CSR interface is a 32-bit Avalon-MM slave of fixed address width; if you do not need this feature, you can disable it to save area. This interface is clocked by csr_clk, which is the same as afi_clk, and is always synchronous relative to the main data slave interface. Controller External Interfaces The following table lists the controller’s external interfaces. Table 5-11: Summary of Controller External Interfaces Interface Name Display Name Type Description Clock and Reset Interface Clock and Reset Interface Clock and Reset Interface AFI (1) Clock and reset generated by UniPHY to the controller. Avalon-ST Data Slave Interface Altera Corporation Functional Description—HPC II Controller Send Feedback
emi_rm_004 2013.12.16 Controller External Interfaces 5-15 Interface Name Display Name Type Description Command Channel Avalon-ST Data Slave Interface Avalon-ST (2) Address and command channel for read and write, single command single data (SCSD). Write Data Channel Avalon-ST Data Slave Interface Avalon-ST (2) Write Data Channel, single command multiple data (SCMD). Read Data Channel Avalon-ST Data Slave Interface Avalon-ST (2) Read data channel, SCMD with read data error response. Controller-PHY Interface AFI 3.0 AFI Interface AFI (1) Interface between controller and PHY. Memory Side-Band Signals Self Refresh (Low Power) Interface Self Refresh (Low Power) Interface Avalon Control & Status Interface (2) SDRAM-specific signals to place memory into low-power mode. User-Controller Refresh Interface User-Controller Refresh Interface Avalon Control & Status Interface (2) SDRAM-specific signals to request memory refresh. Configuration and Status Register (CSR) Interface CSR Configuration and Status Register Interface Avalon-MM (2) Enables on-the-fly configuration of memory timing parameters, address widths, and controller behaviour. Notes: 1. For information about AFI signals, refer to AFI 3.0 Specification in the Functional Description - UniPHY chapter. 2. For information about Avalon signals, refer to Avalon Interface Specifications. Related Information • Avalon Interface Specifications • Functional Description - UniPHY Functional Description—HPC II Controller Altera Corporation Send Feedback
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Functional Description -- HPC II Controller, External Memory ... - Altera

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