Functional Description -- HPC II Controller, External Memory ... - Altera

emi_rm_004
2013.12.16
Local Interface Signals
5-23
Signal Name
local_self_
rfsh_chip
local_self_
rfsh_req
local_init_done
local_cal_
success
local_cal_fail
avl_rdata[] (9)
avl_rdata_
error (10)
avl_rdata_
valid (11)
Direction
Input
Output
Output
Output
Output
Output
Output
Description
Controls which chip to issue the user refresh to. The IP core uses this
active high signal with local_self_rfsh_req. This signal is as
wide as the memory chip select. This signal asserts a high value to each
bit that represents the refresh for the corresponding memory chip.
For example: If local_self_rfsh_chip signal is assigned with
a value of 4’b0101, the controller refreshes the memory chips 0 and
2, and memory chips 1 and 3 are not refreshed.
User control of the self-refresh feature. If you turn on Enable Self-
Refresh Controls, you can request that the controller place the memory
devices into a self-refresh state by asserting this signal. The controller
places the memory in the self-refresh state as soon as it can without
violating the relevant timing parameters and responds by asserting
local_self_rfsh_ack. You can hold the memory in the selfrefresh
state by keeping this signal asserted. You can release the
memory from the self-refresh state at any time by deasserting local_
self_rfsh_req and the controller responds by deasserting local_
_self_rfsh_ack when it has successfully brought the memory
out of the self-refresh state.
When the memory initialization, training, and calibration are complete,
the PHY sequencer asserts ctrl_usr_mode_rdy to the memory
controller, which then asserts this signal to indicate that the memory
interface is ready for use.
When the memory initialization, training, and calibration completes
successfully, the controller asserts this signal coincident with local_
init_done to indicate the memory interface is ready for use.
When the memory initialization, training, or calibration fails, the
controller asserts this signal to indicate that calibration failed. The
local_init_done signal will not assert when local_cal_fail
asserts.
Read data bus. The width of avl_rdata is twice that of the memory
data bus for a full rate controller; four times the memory data bus for
a half rate controller. If Generate power-of-2 data bus widths for
Qsys and SOPC Builder is enabled, the width is rounded down to the
nearest power of 2.
Asserted if the current read data has an error. This signal is only
available if you turn on Enable Error Detection and Correction Logic.
The controller asserts this signal with the avl_rdata_valid signal.
If the controller encounters double-bit errors, no correction is made
and the controller asserts this signal.
Read data valid signal. The avl_rdata_valid signal indicates that
valid data is present on the read data bus.
Functional Description—HPC II Controller
Altera Corporation
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